Soft errors induced by high energy particles have been a severe concern in integrated circuits. Especially in advanced nanoscale technology nodes, the phenomenon of multi-node-upset caused by charge sharing is becoming a crucial issue. However, this problem remains a challenge as there are only few mitigation methods. This brief demonstrates a cost-efficient latch named CROUT featuring double-node-upset tolerance. Integrating coupled Schmitt-triggers and four always-on high-threshold transistors, CROUT is highly reliable in the presence of double-node-upset. To further validate this, a test chip was fabricated in the 28nm CMOS process and tested in a heavy-ion radiation environment. The experimental results indicated that the radiation tolerance is about 2x higher than the standard latches. Moreover, compared to other state-of-the-art multi-node-upset tolerant latches, its power-delay-product (PDP) is reduced by ~6x. The results show that our proposed latch is highly reliable and cost-effective for the space application, which further can be made into a standard cell to be integrated into large-scale circuits.

中文翻译：

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用于航天应用的 28nm CMOS 中具有双节点扰动容限的坚固耐用锁存器

由高能粒子引起的软错误一直是集成电路中的一个严重问题。特别是在先进的纳米级技术节点中，由电荷共享引起的多节点扰乱现象正成为一个至关重要的问题。然而，这个问题仍然是一个挑战，因为只有很少的缓解方法。这个简短的演示名为CROUT配备双节点心烦容忍一个具有成本效益的锁存器。集成了耦合施密特触发器和四个始终开启的高阈值晶体管，CROUT 在存在双节点扰动的情况下非常可靠。为了进一步验证这一点，测试芯片采用 28nm CMOS 工艺制造，并在重离子辐射环境中进行测试。实验结果表明，辐射容限比标准锁存器高约 2 倍。而且，相比状态的最先进的其他多节点加厚宽容锁存器，其功率 - 延迟 - 产物（PDP）是通过6倍〜减少。结果表明，我们提出的锁存器对于空间应用具有高度的可靠性和成本效益，可以进一步制成标准单元以集成到大规模电路中。