This brief presents the unique capabilities of the multimode Dual Mode Logic (DML) design technique to define run-time adaptive datapaths to overcome process and environmental (i.e., temperature and voltage) variations. A proof-of-concept benchmark circuit is designed and fabricated in 65 nm technology. Measurements on 10 test chips, while considering supply voltages spanning 0.6V to 1.2V and temperature variations ranging from -40 °C to 125 °C confirm the effectiveness of this approach to compensate for severe process, voltage and temperature (PVT) variations.

中文翻译：

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PVT 感知数据路径的多模双模逻辑的芯片评估


本简介介绍了多模式双模式逻辑 (DML) 设计技术的独特功能，用于定义运行时自适应数据路径，以克服过程和环境（即温度和电压）变化。采用 65 nm 技术设计和制造概念验证基准电路。对 10 个测试芯片进行的测量，同时考虑了 0.6V 至 1.2V 的电源电压以及 -40 °C 至 125 °C 的温度变化，证实了该方法对于补偿严重的工艺、电压和温度 (PVT) 变化的有效性。