This brief presents an all-digital low dropout regulator (DLDO) with high regulating resolution and fast transient tracking by combining novel interval-searching algorithm and recover acceleration techniques. By bringing forth an enhanced interval-searching algorithm (ISA) with 9-bit register regulating precision, the output can be stabilized within 8 cycles when the load changes. A recover acceleration (RA) technique is proposed to improve the transient response and stability. The DLDO is fabricated with standard 180-nm CMOS process. The proposed DLDO needs 390 pF output capacitance and can provide as much as 170 mA load current. The measured load regulation is 0.11 mV/mA at 0.9 V output with 160 mA load current range. The maximum current efficiency is up to 99.71%. The two FOMs of 2.03 ps and 0.362 pF are also achieved to illustrate the merits of this design.

中文翻译：

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100 MHz、0.8 至 1.1 V、170 mA 数字 LDO，在 180-nm CMOS 中具有 8 周期平均稳定时间和 9 位调节分辨率

本简介通过结合新颖的区间搜索算法和恢复加速技术，介绍了一种具有高调节分辨率和快速瞬态跟踪的全数字低压差稳压器 (DLDO)。通过引入具有9位寄存器调节精度的增强型区间搜索算法(ISA)，负载变化时输出可在8个周期内稳定。提出了一种恢复加速（RA）技术来改善瞬态响应和稳定性。DLDO 采用标准 180 纳米 CMOS 工艺制造。建议的 DLDO 需要 390 pF 的输出电容，并可提供高达 170 mA 的负载电流。测得的负载调节率为 0.11 mV/mA​​，输出电压为 0.9 V，负载电流范围为 160 mA。最大电流效率高达 99.71%。2.03 ps 和 0 的两个 FOM。