We combine 2-tap feed-forward amplitude equalization with phase equalization by 4-tap integrated pulse-width modulation. In a $\text{V}_{\mathbf {SS}}$ -terminated transmitter, amplitude equalization is selected for pull-up data transmission, and phase equalization for pull-down data transmission, and the strength of equalization can be controlled depending on channel losses. This combines the strength of amplitude equalization with the energy efficiency of phase equalization. A prototype quarter-rate transmitter for memory interfaces, fabricated in a 65nm CMOS process, performed single-ended signaling at a data-rate of 16Gb/s/pin over a channel with a loss of 14.7dB. Its energy efficiency is 1.04pJ/bit/pin and the figure-of-merit is 0.070pJ/bit/pin/dB.

中文翻译：

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用于存储器接口的四分之一速率发送器中幅度和相位均衡的数据相关选择

我们通过 4 抽头集成脉宽调制将 2 抽头前馈幅度均衡与相位均衡相结合。在$\text{V}_{\mathbf {SS}}$终端发射机中，上拉数据传输选择幅度均衡，下拉数据传输选择相位均衡，均衡强度可以控制取决于通道损耗。这结合了幅度均衡的强度和相位均衡的能量效率。用于存储器接口的原型四分之一速率发射器采用 65 纳米 CMOS 工艺制造，以 16Gb/s/pin 的数据速率在一个通道上执行单端信号传输，损耗为 14.7dB。其能效为 1.04pJ/bit/pin，品质因数为 0.070pJ/bit/pin/dB。