We propose a logic synthesis methodology with a novel low-power circuit structure for ternary logic. The proposed methodology synthesizes a ternary function as a ternary logic gate using carbon nanotube field-effect transistors (CNTFETs). The circuit structure uses the body effect to mitigate the excessive power consumption for the third logic value. Energy-efficient ternary logic circuits are designed with a combination of synthesized low-power ternary logic gates. The proposed methodology is applicable to both unbalanced (0, 1, 2) and balanced (−1, 0, 1) ternary logic. To verify the improvement in energy efficiency, we have designed various ternary arithmetic logic circuits using the proposed methodology. The proposed ternary full adder has a significant improvement in the power-delay product (PDP) over previous designs. Ternary benchmark circuits have been designed to show that complex ternary functions can be designed to more efficient circuits with the proposed methodology.

中文翻译：

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一种低功耗三元逻辑电路的逻辑综合方法

我们提出了一种逻辑综合方法，具有用于三元逻辑的新型低功耗电路结构。所提出的方法使用碳纳米管场效应晶体管 (CNTFET) 将三元函数合成为三元逻辑门。该电路结构利用体效应来减轻第三逻辑值的过度功耗。高能效三元逻辑电路采用合成低功耗三元逻辑门的组合设计。所提出的方法适用于不平衡 (0, 1, 2) 和平衡 (-1, 0, 1) 三元逻辑。为了验证能效的提高，我们使用所提出的方法设计了各种三元算术逻辑电路。与以前的设计相比，建议的三元全加器在功率延迟积 (PDP) 方面有显着改进。