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Low-Voltage Gate-Leakage-Based Timer Using an Amplifier-Less Replica-Bias Switching Technique in 55-nm DDC CMOS
IEEE Open Journal of Circuits and Systems ( IF 2.4 ) Pub Date : 2020-07-07 , DOI: 10.1109/ojcas.2020.3007393
Atsuki Kobayashi , Kiichi Niitsu

Energy-efficient timer circuits are required in numerous applications for periodic operations, such as performing measurements and communicating data. In this paper, we present a gate-leakage-based timer that utilizes an amplifier-less replica-bias switching technique to generate a stable frequency, which can operate at a low supply voltage. To guarantee a stable oscillation frequency in a small circuit area, the proposed design adopts an architecture that discharges a pre-charged capacitor through a resistive element (gate-leaking MOS capacitor) with a low-leakage switch. In the proposed switching technique, the low-voltage timer operates by tracking the discharging terminal of the capacitor and biasing the reference voltage of the switch unit, thereby enabling the minimization of the leakage current without the need for analog amplifier circuits. The high supply sensitivity of the timer is addressed by regulating the supply voltage using a native NMOS header (NNH). The proposed design is fabricated using the 55-nm deeply depleted channel (DDC) CMOS technology, which has a strong body coefficient and occupies an active circuit area of 0.0022 mm 2 . The measurements show that the proposed design can achieve an energy-per-cycle value of 25 pJ/cycle at a supply voltage of 350 mV when body biasing is applied. The measured Allan deviation floor is 200 ppm at room temperature. The timer exhibits an average temperature sensitivity of 810 ppm/°C for four samples. Moreover, a reduction in the supply sensitivity by a factor of 26 using the NNH is demonstrated in an active circuit area of 0.0034 mm 2 .

中文翻译:

在55 nm DDC CMOS中使用无放大器偏置偏置切换技术的低压栅极漏电定时器

在许多应用中需要节能定时器电路来进行周期性操作,例如执行测量和传输数据。在本文中,我们介绍了一种基于门泄漏的定时器,该定时器利用无放大器的复制偏置开关技术来产生稳定的频率,该频率可以在低电源电压下工作。为了确保在较小的电路区域内保持稳定的振荡频率,所提出的设计采用了一种架构,该架构通过具有低漏电开关的电阻性元件(栅漏MOS电容器)对预充电的电容器进行放电。在所提出的开关技术中,低压定时器通过跟踪电容器的放电端子并偏置开关单元的参考电压来工作,从而能够在不需要模拟放大器电路的情况下使泄漏电流最小化。通过使用本机NMOS标头(NNH)调节电源电压,可以解决计时器的高电源灵敏度问题。拟议的设计是使用55纳米深耗尽沟道(DDC)CMOS技术制造的,该技术具有很强的主体系数,并占用0.0022 mm的有源电路面积 2 。测量结果表明,当施加人体偏置时,在350 mV的电源电压下,提出的设计可以实现25 pJ /周期的每周期能量值。室温下测得的艾伦偏差底限为200 ppm。该计时器对四个样品的平均温度敏感度为810 ppm /°C。此外,在有源电路面积为0.0034 mm 2的情况下,使用NNH可使电源灵敏度降低26倍 。
更新日期:2020-08-28
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