Four calibration algorithms based on the order statistics about capacitive mismatch are proposed for successive approximation register (SAR) analog‐to‐digital converter (ADC). An 18‐bit split capacitive SAR ADC architecture with redundant bits was used to verify the four calibration algorithms proposed. The main dynamic parameters of the SAR ADC were simulated in MATLAB by 500 Monte‐Carlo runs with a standard deviation of 0.1% (σ₀/C₀ = 0.001). And the simulation results of sorting and regrouping method II (SRGII) show that a 21.64‐dB enhancement of spurious‐free dynamic range (SFDR) and a 3.33‐bit improvement of effective number of bits (ENOB) have achieved respectively, whereas the simulation results of sorting and re‐exchanging method I (SREI) show that a 21.64‐dB enhancement of SFDR and a 3.34‐bit improvement of ENOB have achieved, respectively

中文翻译：

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四种创新的校准算法，可解决18位冗余分割SAR ADC中的电容失配问题

针对逐次逼近寄存器（SAR）模数转换器（ADC），提出了四种基于电容不匹配的阶跃统计量的校准算法。具有冗余位的18位拆分电容式SAR ADC体系结构用于验证提出的四种校准算法。在SAR ADC的主要动态参数在MATLAB进行了模拟由500蒙特卡洛运行用的0.1％的标准偏差（σ ₀ / C ^ ₀  = 0.001）。排序和重组方法II（SRGII）的仿真结果表明，分别实现了21.64 dB的无杂散动态范围（SFDR）增强和有效位数（ENOB）的3.33位改进，而仿真排序和重新交换方法I（SREI）的结果表明，分别实现了SFDR的21.64 dB增强和ENOB的3.34位增强。