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CNFET based design of unbalanced ternary circuits using efficient shifting literals
Microelectronics Journal ( IF 1.9 ) Pub Date : 2020-08-25 , DOI: 10.1016/j.mejo.2020.104869
Trapti Sharma , Laxmi Kumre

Multi-valued logic design provides the benefit of increased integration by reducing the interconnections which is the main source of power dissipation in the VLSI chip. As compared to conventional binary logic representation, ternary logic representation helps to represent more amount of information over the same number of digits. Hence this work presents the design of ternary adder, subtractor, multiplier and parallel adder/subtractor with enhanced performance in carbon nanotube field effect transistor (CNFET) technology. The addition and subtraction operations are set into a single unit, exploiting the advantage of ternary logic to increase the processing capability of the module. The presence of symmetricity among single shift and dual shift operators while realizing addition/subtraction operation further favors the combing of adder/subtractor blocks. Then 4-stage parallel adder/subtractor is designed. Further single-trit and multi-trit multiplier circuits are also implemented by employing the proposed adder and multiplier units. All the proposed arithmetic designs are derived from the proposed ternary multiplexer and shifting operator circuits. To test the efficiency of proposed circuits, the simulations are conducted on 32 nm CNFET technology using Synopsis HSPICE simulator. In the proposed methodology reduction in power consumption of 38% for combined adder/subtraction block and 40% for parallel adder/subtractor unit is obtained. Furthermore, for the multi trit adder/subtractor and multiplier designs, the maximum power delay product (PDP) improvement up to 66% is achieved.



中文翻译:

使用有效移位字面量的基于CNFET的不平衡三元电路设计

多值逻辑设计通过减少互连(这是VLSI芯片功耗的主要来源)而提供了增强集成的优势。与常规二进制逻辑表示相比,三进制逻辑表示有助于在相同位数上表示更多信息。因此,这项工作提出了在碳纳米管场效应晶体管(CNFET)技术中具有增强性能的三进制加法器,减法器,乘法器和并行加法器/减法器的设计。加法和减法运算被设置为一个单元,从而利用三元逻辑的优势来增加模块的处理能力。在实现加/减运算的同时,单移位和双移位运算符之间存在对称性,这进一步有利于加法器/减法器块的组合。然后设计了四级并行加法器/减法器。通过采用建议的加法器和乘法器单元,还可以实现其他的单触发和多触发乘法器电路。所有拟议的算法设计均源自拟议的三元复用器和移位运算器电路。为了测试所提出电路的效率,使用Synopsis HSPICE仿真器在32 nm CNFET技术上进行了仿真。在所提出的方法中,组合加法器/减法器模块的功耗降低了38%,并行加法器/减法器单元的功耗降低了40%。此外,对于多重三态加法器/减法器和乘法器设计,

更新日期:2020-09-10
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