Using dynamic partial reconfiguration (DPR) feature in field-programmable gate array (FPGA) systems seems inevitable by considering the tremendous benefits, such as reduced cost and power. Nowadays, manual floorplanning is one of the difficulties in implementing DPR systems, which relies on the designer’s views and his command over designing the concepts for arranging the modules on the physical layout of the FPGA more efficiently, as the results of floorplanning can influence the next stages, such as the placement. In other words, placement and floorplanning that are separately conducted in the today’s tools are interdependent and the floorplanning results play a role in the placement and vice versa. This article aimed to propose a method for conducting floorplanning and placement simultaneously in DPR systems according to the genetic algorithm (GA). The proposed algorithm was tested on 20 largest MCNC benchmark circuits with DPR-support capability. Based on the results, wirelength and critical path delay improved by 14% and 17%, respectively, compared with Xilinx’s early access partial reconfiguration design flow (EAPR). However, area and runtime increased by about 2% and 8%, respectively. The proposed method was also compared with other research that uses B* tree and simulated annealing algorithm. The results showed that our proposed algorithm is competitive in various parameters with other research.

中文翻译：

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基于遗传算法的动态部分重配置现场可编程门阵列中的自动和同时布局规划和布局

考虑到成本和功耗降低等巨大优势，在现场可编程门阵列 (FPGA) 系统中使用动态部分重配置 (DPR) 功能似乎是不可避免的。如今，手动布局规划是实现 DPR 系统的难点之一，它依赖于设计者的观点和他对设计概念的指挥，以便更有效地在 FPGA 的物理布局上安排模块，因为布局规划的结果会影响下一步阶段，例如安置。换句话说，在当今工具中单独进行的布局和布局规划是相互依赖的，布局规划结果在布局中发挥作用，反之亦然。本文旨在提出一种根据遗传算法 (GA) 在 DPR 系统中同时进行布局规划和布局的方法。所提出的算法在具有 DPR 支持能力的 20 个最大的 MCNC 基准电路上进行了测试。根据结果​​，与赛灵思的早期访问部分重配置设计流程 (EAPR) 相比，线长和关键路径延迟分别提高了 14% 和 17%。然而，面积和运行时间分别增加了约 2% 和 8%。该方法还与其他使用B*树和模拟退火算法的研究进行了比较。结果表明，我们提出的算法在各种参数上与其他研究相比具有竞争力。与赛灵思的早期访问部分重配置设计流程 (EAPR) 相比，线长和关键路径延迟分别提高了 14% 和 17%。然而，面积和运行时间分别增加了约 2% 和 8%。该方法还与其他使用B*树和模拟退火算法的研究进行了比较。结果表明，我们提出的算法在各种参数上与其他研究相比具有竞争力。与赛灵思的早期访问部分重配置设计流程 (EAPR) 相比，线长和关键路径延迟分别提高了 14% 和 17%。然而，面积和运行时间分别增加了约 2% 和 8%。该方法还与其他使用B*树和模拟退火算法的研究进行了比较。结果表明，我们提出的算法在各种参数上与其他研究相比具有竞争力。