Routing is a crucial step in Field Programmable Gate Array (FPGA) physical design, as it determines the routes of signals in the circuit, which impacts the design implementation quality significantly. It can be very time-consuming to successfully route all the signals of large circuits that utilize many FPGA resources. Attempts have been made to shorten the routing runtime for efficient design exploration while expecting high-quality implementations. In this work, we elaborate on the connection-based routing strategy and algorithmic enhancements to improve the serial FPGA routing. We also explore a recursive partitioning-based parallelization technique to further accelerate the routing process. To exploit more parallelism by a finer granularity in both spatial partitioning and routing, a connection-aware routing bounding box model is proposed for the source-sink connections of the nets. It is built upon the location information of each connection’s source, sink, and the geometric center of the net that the connection belongs to, different from the existing net-based routing bounding box that covers all the pins of the entire net. We present that the proposed connection-aware routing bounding box is more beneficial for parallel routing than the existing net-based routing bounding box. The quality and runtime of the serial and multi-threaded routers are compared to the router in VPR 7.0.7. The large heterogeneous Titan23 designs that are targeted to a detailed representation of the Stratix IV FPGA are used for benchmarking. With eight threads, the parallel router using the connection-aware routing bounding box model reaches a speedup of 6.1× over the serial router in VPR 7.0.7, which is 1.24× faster than the one using the existing net-based routing bounding box model, while reducing the total wire-length by 10% and the critical path delay by 7%.

中文翻译：

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通过算法增强和连接感知并行化加速 FPGA 路由

布线是现场可编程门阵列 (FPGA) 物理设计中的关键步骤，因为它决定了电路中信号的路径，从而显着影响设计实现质量。成功路由使用许多 FPGA 资源的大型电路的所有信号可能非常耗时。已经尝试缩短路由运行时间以进行有效的设计探索，同时期望高质量的实现。在这项工作中，我们详细阐述了基于连接的路由策略和算法增强，以改进串行 FPGA 路由。我们还探索了一种基于递归分区的并行化技术，以进一步加速路由过程。为了在空间分区和路由中通过更精细的粒度来利用更多的并行性，针对网络的源-汇连接，提出了一种连接感知路由边界框模型。它建立在每个连接的源、汇和连接所属网络的几何中心的位置信息之上，不同于现有的覆盖整个网络所有引脚的基于网络的路由边界框。我们提出，所提出的连接感知路由边界框比现有的基于网络的路由边界框更有利于并行路由。串行和多线程路由器的质量和运行时间与 VPR 7.0.7 中的路由器进行了比较。针对 Stratix IV FPGA 的详细表示的大型异构 Titan23 设计用于基准测试。用八根线，