As design complexity is increased exponentially, electronic design automation (EDA) tools are essential to reduce design efforts. However, the analog layout design has still been done manually for decades because it is a sensitive and error-prone task. Tool-generated layouts are still not well-accepted by analog designers due to the performance loss under non-ideal effects. Most previous works focus on adding more layout constraints on the analog placement. Routing the nets is thus considered as a trivial step that can be done by typical digital routing methodology, which is to use vias to connect every horizontal and vertical lines. Those extra vias will significantly increase the wire loads and degrade the circuit performance. Therefore, in this article, a wire load oriented analog routing methodology is proposed to reduce the number of layer changing of each routing net. Wire load is considered in the optimization goal as well as the wire length to keep the circuit performance after layout, while the analog layout constraints like symmetry and length matching are still satisfied during routing. As shown in the experimental results, this approach significantly reduces the wire load and performance loss after layout with little overhead on wire length.

中文翻译：

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具有匹配约束的面向线负载的模拟路由

随着设计复杂性成倍增加，电子设计自动化 (EDA) 工具对于减少设计工作至关重要。然而，模拟布局设计几十年来仍然是手动完成的，因为它是一项敏感且容易出错的任务。由于在非理想效果下的性能损失，工具生成的布局仍未被模拟设计人员很好地接受。大多数以前的工作都集中在模拟布局上添加更多的布局约束。因此，布线网络被认为是一个简单的步骤，可以通过典型的数字布线方法完成，即使用通孔连接每条水平和垂直线。这些额外的过孔会显着增加导线负载并降低电路性能。因此，在这篇文章中，提出了一种面向线路负载的模拟路由方法，以减少每个路由网络的层数变化。优化目标中考虑了线负载以及线长度，以保持布局后的电路性能，而在布线过程中仍然满足对称性和长度匹配等模拟布局约束。如实验结果所示，这种方法显着降低了布线后的布线负载和性能损失，而布线长度上的开销很小。