In this study a new structure was presented to design and simulate a considerably low power and high-speed 4-bit flash analogue to digital converter based on TSMC 0.18 μm complementary metal-oxide semiconductor (CMOS) technology. In this structure, in order to reduce the power consumption in the proposed comparator, the reference voltage was removed and replaced with the threshold voltage of CMOS transistors. This method has reduced the power consumption greatly. Additionally, by employing reversible logic in the 2:1 multiplier, the power consumption and the number of stages were dropped and obtaining a faster converter was considered as the other breakthrough. The simulation was carried out in 1.8 V supply voltage and power consumption of 330 μW while the sampling rate was equal to 2GSample/s.

中文翻译：

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低功耗高速4位闪存模数转换器的方法

在这项研究中，提出了一种新结构，用于设计和仿真基于TSMC 0.18μm互补金属氧化物半导体（CMOS）技术的低功耗，高速4位闪存模数转换器。在这种结构中，为了减少所提出的比较器的功耗，去除了基准电压，并用CMOS晶体管的阈值电压代替了基准电压。该方法大大降低了功耗。此外，通过在2：1乘法器中采用可逆逻辑，功耗和级数得以降低，而获得更快的转换器被视为另一项突破。仿真是在1.8 V电源电压和330μW功耗下进行的，而采样速率等于2GSample / s。