In this study, an InAs channel-based triple gate spin-field effect transistor (FET) model is proposed. The proposed triple-gate spin-FET offers a high density of integration, consumes low power and offers very high switching speed. By incorporating the suitable parameters like channel length, spin diffusion length, channel resistance and junction polarisation, the modelled triple gate spin-FET is then used to implement 3-input XOR, 3-input XNOR and majority gate functions. The designs of 3-input XOR and majority gates were achieved keeping in view that the sum operation of a 1-bit full adder is obtained through XOR gate and the carry operation of 1-bit full adder is obtained through majority gate. Therefore, for designing a 1-bit full adder, only two spin-FETs will be required which signifies the compact nature of the design. In addition, a 2-bit ripple adder is designed with cascading two 1-bit full-adders. Finally, a comparative analysis of the proposed gates and 1-bit full adder with the reported work and conventional CMOS design was carried out in terms of employed number of devices, power consumption and speed. The analysis shows that proposed gates/adder offer better performance than the reported work and conventional CMOS designs.

中文翻译：

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三栅极自旋FET建模和基于三栅极自旋FET的二进制加法器设计

在这项研究中，提出了一种基于InAs沟道的三栅极自旋场效应晶体管（FET）模型。提出的三栅极自旋FET具有高集成度，功耗低且开关速度非常快的特点。通过合并合适的参数，例如沟道长度，自旋扩散长度，沟道电阻和结极化，建模的三栅极自旋FET随后可用于实现3输入XOR，3输入XNOR和多数栅极功能。鉴于通过XOR门获得1位全加法器的求和运算以及通过多数门获得1位全加法器的进位运算，因此实现了3输入XOR和多数门的设计。因此，对于设计1位全加法器，仅需要两个自旋FET，这表明设计的紧凑性。此外，一个2位波纹加法器设计为级联两个1位全加法器。最后，根据所使用的器件数量，功耗和速度，对所报告的门和1位全加器以及所报告的工作和常规CMOS设计进行了比较分析。分析表明，与报告的工作和传统的CMOS设计相比，提出的门/加法器具有更好的性能。