A fixed-width multiplier receives two n-bit operands and generates an approximate n-bit product as the output. It truncates part of the partial products and employs an appropriate error compensation circuit in order to reduce the approximation error. In this study, a new error compensation circuit for the fixed-width multiplier has been proposed which utilises the correction vector (CV) and modified minor CV. The proposed error compensation circuit is capable of minimising both the mean error and the mean-square error. Post-synthesis results for 16-bit of fixed-width multiplier demonstrate that the proposed circuit has 3.50, 39.24, 42.91 and 44.91% reduced delay, area, power consumption and power-delay product when compared with the existing design reported in the literature.

中文翻译：

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固定宽度乘法器的省电补偿电路

定宽乘法器接收两个n位操作数，并生成一个近似n位乘积作为输出。它会截去部分乘积的一部分，并采用适当的误差补偿电路以减小近似误差。在这项研究中，提出了一种新的用于定宽乘法器的误差补偿电路，该电路利用校正矢量（CV）和修改的次要CV。所提出的误差补偿电路能够最小化均值误差和均方误差。16位固定宽度乘法器的合成后结果表明，与文献中报道的现有设计相比，该电路的延迟，面积，功耗和功耗乘积减少了3.50％，39.24、42.91和44.91％。