This study presents a negative bias temperature instability (NBTI) mitigation design technique for CMOS 6T-static random access memory (6T-SRAM) cells. The proposed approach is based on transistor sizing technique. It consists of sizing the nMOS access transistors of the cell to alleviate NBTI ageing occurring in its pMOS pull-up transistors threatening the cell stability. Once the access transistors are sized for a better hold static noise margin under NBTI, the other transistors of the 6T-SRAM cell could be properly sized for improved read stability and write-ability.

中文翻译：

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CMOS 6T-SRAM单元的尺寸可用于NBTI老化缓解

这项研究提出了一种用于CMOS 6T静态随机存取存储器（6T-SRAM）单元的负偏压温度不稳定性（NBTI）缓解设计技术。所提出的方法基于晶体管尺寸确定技术。它包括确定单元的nMOS存取晶体管的大小，以减轻在其pMOS上拉晶体管中出现的NBTI老化，从而威胁单元稳定性。一旦将访问晶体管的尺寸确定为在NBTI下能更好地保持静态噪声容限，则6T-SRAM单元的其他晶体管的尺寸将得到适当调整，以提高读取稳定性和可写性。