Based on a standard 0.18μm BiCMOS process, a 12 bit 2GSps ADC is achieved using time-interleaved pipelined architecture in this work. The DC offset caused by the mismatch of ADC channels is removed due to the application of digital calibration technology, which improves the performance of the ADC. The power supply voltage is 1.8 V and the power consumption is 100 mW for each lane. The measurement results indicated that the circuit in this paper can be used in multi-channel time-domain interleaved pipelined ADC architecture to achieve a 2GSps ultra high speed ADC.

中文翻译：

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具有超高速采样的时间交错流水线ADC

在这项工作中，基于标准的0.18μmBiCMOS工艺，使用时间交错流水线架构实现了12位2GSps ADC。由于数字校准技术的应用，消除了由ADC通道不匹配引起的DC偏移，从而改善了ADC的性能。每个通道的电源电压为1.8 V，功耗为100 mW。测量结果表明，该电路可用于多通道时域交错流水线ADC体系结构中，以实现2GSps超高速ADC。