this brief presents a new 11-bit 1.2 ​GS/s hybrid digital to analog converter (DAC) simulated in 65 ​nm CMOS technology. In this new structure, a combination of a resistor ladder and current sources is used to realize the 11-bit DAC structure. The current sources are connected to different nodes of the resistor ladder in a logical way. In this situation, equal current sources make different voltage values. Furthermore, the complicated binary to thermometer decoders are exchanged with the basic digital logics. This new technique remarkably reduces the number of current sources needed for realization an 11-bit DAC and leads to the circuit dissipates just 4.68 ​mW power while the power supply is 1.2 ​V. Also, the occupied area is 0.0061 ​mm². Post layout simulation results indicate that the spurious-free dynamic range (SFDR) is more than 70 ​dB over 600 ​MHz Nyquist BW. The INL and DNL parameters are also obtained better than 1.2 LSB and 1 LSB, respectively.

本简介介绍了一种采用65 nm CMOS技术模拟的新型11位1.2 GS / s混合数模转换器（DAC）。在这种新结构中，电阻梯形图和电流源的组合用于实现11位DAC结构。电流源以逻辑方式连接到梯形电阻器的不同节点。在这种情况下，相等的电流源会产生不同的电压值。此外，将复杂的二进制至温度计解码器与基本数字逻辑进行交换。这项新技术显着减少了实现11位DAC所需的电流源数量，并导致电路在电源为1.2V时仅消耗4.68 mW的功率。另外，占用面积为0.0061毫米²。布局后的仿真结果表明，在600 MHz奈奎斯特带宽上，无杂散动态范围（SFDR）超过70 dB。还分别获得了优于1.2 LSB和1 LSB的INL和DNL参数。