This paper first presents novel approximate reverse carry full adder (ARFA) circuits where the weight of the input carry is more than that of the output carry. Using the proposed ARFAs and conventional full adders, new approximate reverse carry propagate adder (ARCAs) architectures are presented where the carry propagates in a counter manner. The proposed ARCA provides trade-off in accuracy and performance depending on the number of ARFAs used. Further, novel accuracy reconfigurable reverse carry propagate adders are proposed that provide approximate sum with high energy efficiency and can also deliver 100% accurate sum with small performance penalty. For comparative analysis, the proposed and existing adders are modeled in Verilog and synthesized via Synopsys Design Compiler with 65 nm PDK. The synthesis results of the proposed 16-bit ARCA-II show 9.93% reduced energy consumption over the existing. Finally, the Gaussian smoothing filter (GSF) embedded with the proposed adder shows 12.15% reduced energy consumption with an acceptable image quality (1.64 dB loss in PSNR) over the GSFs with the existing adder.

本文首先介绍了新颖的近似反向进位全加法器（ARFA）电路，其中输入进位的权重大于输出进位的权重。使用提出的ARFA和常规的全加法器，提出了新的近似反向进位传播加法器（ARCA）架构，其中进位以相反的方式传播。所提出的ARCA根据所使用的ARFA的数量在准确性和性能上进行权衡。此外，提出了新颖的精度可重构的反向进位传播加法器，其提供具有高能量效率的近似和，并且还可以以小的性能损失来提供100％的精确和。为了进行比较分析，在Verilog中对建议的加法器和现有的加法器进行了建模，并通过Synopsys Design Compiler使用65 nm PDK进行了合成。拟议的16位ARCA-II的综合结果表明，与现有技术相比，能耗降低了9.93％。最后，与现有加法器相比，嵌入拟议的加法器的高斯平滑滤波器（GSF）的能耗降低了12.15％，图像质量可接受（PSNR损失1.64 dB）。