The SPARC instruction set architecture (ISA) has been used in various processors in workstations, embedded systems, and in mission-critical industries such as aviation and space engineering. Hence, it is important to provide formal frameworks that facilitate the verification of hardware and software that run on or interface with these processors. In this work, we give the first formal model for multi-core SPARC ISA and Total Store Ordering (TSO) memory model in Isabelle/HOL. We present two levels of modelling for the ISA: The low-level ISA model, which is executable, covers many features specific to SPARC processors, such as delayed-write for control registers, windowed general registers, and more complex memory access. We have tested our model extensively against a LEON3 simulation board, the test covers both single-step executions and sequential execution of programs. We also prove some important properties for our formal model, including a non-interference property for the LEON3 processor. The high-level ISA model is an abstraction of the low-level model and it provides an interface for memory operations in multi-core processors. On top of the high-level ISA model, we formalise two TSO memory models: one is an adaptation of the axiomatic SPARC TSO model (Sindhu et al. in Formal specification of memory models, Springer, Boston, 1992; SPARC in The SPARC architecture manual version 8, 1992. http://gaisler.com/doc/sparcv8.pdf), the other is a new operational TSO model which is suitable for verifying execution results. We prove that the operational model is sound and complete with respect to the axiomatic model. Finally, we give verification examples with two case studies drawn from the SPARCv9 manual.

中文翻译：

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SPARC 指令集架构和 TSO 内存模型的 Isabelle/HOL 形式化

SPARC 指令集架构 (ISA) 已被用于工作站、嵌入式系统以及航空航天工程等关键任务行业的各种处理器中。因此，重要的是提供正式的框架，以促进对在这些处理器上运行或与这些处理器接口的硬件和软件的验证。在这项工作中，我们给出了 Isabelle/HOL 中多核 SPARC ISA 和 Total Store Ordering (TSO) 内存模型的第一个正式模型。我们为 ISA 提供了两个级别的建模： 低级 ISA 模型，它是可执行的，涵盖许多特定于 SPARC 处理器的功能，例如控制寄存器的延迟写入、窗口化通用寄存器和更复杂的内存访问。我们已经针对 LEON3 仿真板广泛地测试了我们的模型，该测试涵盖程序的单步执行和顺序执行。我们还证明了我们的形式模型的一些重要属性，包括 LEON3 处理器的非干扰属性。高级ISA模型是低级模型的抽象，它为多核处理器中的内存操作提供了一个接口。在高级 ISA 模型之上，我们形式化了两个 TSO 内存模型：一个是公理化 SPARC TSO 模型的改编版（Sindhu 等人在内存模型的正式规范中，Springer，波士顿，1992 年；SPARC 在 SPARC 架构中手册第 8 版，1992 年。http://gaisler.com/doc/sparcv8.pdf)，另一个是适用于验证执行结果的新操作 TSO 模型。我们证明操作模型相对于公理模型是健全和完整的。最后，