Due to the high defect rate of nanodevices and nanowires in the process of manufacturing, the defect-tolerance mapping in CMOS/nanowire/molecule hybrid (CMOL) circuit is a key step to achieve the correct logic function. However, a high defect rate may reduce the success rate of defect-tolerance mapping because of the shortage of mapping resources. In this paper, a defective cell reuse based defect-tolerance mapping optimization method is proposed to address the mapping problem under limited mapping resources in defective CMOL circuits. First, stuck-at-close defect is analyzed and the constraint of reusing defective cells is proposed. Second, the logic hierarchy based mapping framework is undertaken to improve the mapping success rate and the performance of mapped CMOL circuit. Finally, the method is embedded into Tabu Search (TS) algorithm to verify the feasibility and efficiency. Experimental evaluation on ISCAS benchmark shows that compared with the existing methods, the proposed method has a higher defect-tolerance mapping success rate and a better mapped performance.

由于纳米器件和纳米线在制造过程中的高缺陷率，CMOS /纳米线/分子混合（CMOL）电路中的缺陷容限映射是实现正确逻辑功能的关键步骤。但是，由于映射资源不足，高的缺陷率可能会降低容错映射的成功率。提出了一种基于缺陷单元重用的缺陷容错映射优化方法，以解决缺陷CMOL电路中有限映射资源下的映射问题。首先，分析闭合缺陷，并提出了缺陷单元重用的约束条件。其次，采用基于逻辑层次的映射框架来提高映射成功率和映射的CMOL电路的性能。最后，该方法被嵌入禁忌搜索算法中，以验证其可行性和有效性。对ISCAS基准的实验评估表明，与现有方法相比，该方法具有较高的容错映射成功率和较好的映射性能。