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Variation-tolerant, low-power, and high endurance read scheme for memristor memories
Analog Integrated Circuits and Signal Processing ( IF 1.2 ) Pub Date : 2020-08-10 , DOI: 10.1007/s10470-020-01702-0
V. Ravi , K. Chitra , S. R. S. Prabaharan

Abstract

Reading the memristor memory cell without changing its resistance state is one of the potential problems to be addressed in the memristor-based memory design. This paper presents a novel read scheme that achieves a non-destructive read operation, consumes less power, provides high endurance and adapts itself based on the process variations. The proposed scheme uses built-in self-tuning circuitry to obtain the optimum amplitude and width of the refresh pulse required to completely retrieve the state of the memristor after the read cycle. As the scheme uses refresh pulse only when needed, the scheme saves nearly 50% of average power when compared with a conventional fixed pulse read method. The self-tuning circuits are validated by a generic, accurate, and efficient “voltage threshold adaptive memristor” model. The validation results prove that the proposed tuning circuitry achieves optimum refresh pulse size under various read disturbance faults.

Graphic abstract



中文翻译:

忆阻器存储器的耐变化,低功耗和高耐久性读取方案

摘要

在不改变其忆阻状态的情况下读取忆阻器存储单元是基于忆阻器的存储器设计中要解决的潜在问题之一。本文提出了一种新颖的读取方案,该读取方案可实现无损读取操作,消耗较少的功率,提供较高的耐用性并根据过程变化进行自我调整。所提出的方案使用内置的自调谐电路来获得刷新脉冲的最佳幅度和宽度,以在读取周期后完全恢复忆阻器的状态。由于该方案仅在需要时才使用刷新脉冲,因此与传统的固定脉冲读取方法相比,该方案可节省近50%的平均功率。自调谐电路已通过通用,准确,高效的“电压阈值自适应忆阻器”模型进行了验证。

图形摘要

更新日期:2020-08-11
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