High Level Synthesis (HLS) tools enable application domain experts to implement applications and algorithms on FPGAs. The majority of present FPGA applications is following a stream processing model which is almost entirely implemented statically and not exploiting the benefits enabled by partial reconfiguration. In this paper, we propose a generic approach for implementing and using partial reconfiguration through an HLS design flow for Maxeler platforms. Our flow extracts HLS generated HDL code from the Maxeler compilation process in order to implement a static FPGA infrastructure as well as run-time reconfigurable stream processing modules. As a distinct feature, our infrastructure can accommodate multiple partial modules in a pipeline daisy-chained manner, which aligns directly to Maxeler’s dataflow programming paradigm. The benefits of the proposed flow are demonstrated by a case study of a dynamically reconfigurable video processing pipeline delivering 6.4GB/s throughput.

高级综合（HLS）工具使应用程序领域的专家能够在FPGA上实现应用程序和算法。当前大多数FPGA应用程序都遵循流处理模型，该模型几乎完全是静态实现的，没有利用部分重新配置带来的好处。在本文中，我们提出了一种通过Maxeler平台的HLS设计流程来实现和使用部分重配置的通用方法。我们的流程从Maxeler编译过程中提取HLS生成的HDL代码，以实现静态FPGA基础结构以及运行时可重新配置的流处理模块。作为一项独特功能，我们的基础架构可以以流水线菊花链方式容纳多个部分模块，这直接与Maxeler的数据流编程范例保持一致。