The charging effect generated by the accumulation of negative charges on a mask surface strongly limits the perfect pattern transfer from the mask to the substrate during the plasma etching process, which leads to the deformation of etched features and severely damages the mask pattern. This study first verified that various placements of the holes will result in different distributions of the electric filed (E-field) and the etching rate. This work next shows that the electron angular distribution (EAD) is closely related to the damage to the mask pattern. Based on a reliable modeling framework, the effects of changing the EAD on the distributions of spatial E-field and the etching rate were examined focusing on two adjacent and asymmetrically-shaped mask holes. Specifically, both the E-field strength and the etching rate around the edge of the two mask holes can be greatly reduced by narrowing the EAD, meanwhile, the number of electrons penetrating into the bottom of two holes will be significantly increased. These results will reduce the mask pattern damage and improve the etching of high-aspect-ratio features into a substrate. In the cases of different EADs, the simulated evolution rates of these two mask holes and the E-field strength inside the holes verify these conclusions. The mechanism is discussed in detail. This work will greatly help to optimize the etching technique.

中文翻译：

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探索等离子体蚀刻过程中放置​​和电子角度分布对两个相邻掩模孔的影响

在等离子刻蚀过程中，负电荷在掩膜表面积累所产生的带电效应强烈限制了从掩膜到衬底的完美图案转移，导致蚀刻特征变形并严重损坏掩膜图案。这项研究首先证实了孔的不同放置会导致电场（E场）和蚀刻速率的不同分布。这项工作接下来表明电子角分布 (EAD) 与掩模图案的损坏密切相关。基于可靠的建模框架，研究了改变 EAD 对空间电场分布和蚀刻速率的影响，重点是两个相邻且形状不对称的掩模孔。具体来说，通过缩小EAD可以大大降低E场强度和两个掩模孔边缘周围的蚀刻速率，同时穿透两个孔底部的电子数量将显着增加。这些结果将减少掩模图案损坏并改善高纵横比特征到基板的蚀刻。在不同 EAD 的情况下，这两个掩膜孔的模拟演化速率和孔内的电场强度验证了这些结论。详细讨论了该机制。这项工作将极大地帮助优化蚀刻技术。这些结果将减少掩模图案损坏并改善高纵横比特征到基板的蚀刻。在不同 EAD 的情况下，这两个掩膜孔的模拟演化速率和孔内的电场强度验证了这些结论。详细讨论了该机制。这项工作将极大地帮助优化蚀刻技术。这些结果将减少掩模图案损坏并改善高纵横比特征到基板的蚀刻。在不同 EAD 的情况下，这两个掩膜孔的模拟演化速率和孔内的电场强度验证了这些结论。详细讨论了该机制。这项工作将极大地帮助优化蚀刻技术。