With the rapidly increasing test time of semiconductor testing, the trend is currently toward improving test parallelism by exploiting multi-site testing. However, excessive test I/O channels and test power consumption lead to the degradation of multi-site testing efficiency owing to the limited number of tester I/Os and power capacity. In this paper, we present an advanced low pin count test architecture for efficient multi-site testing in semiconductors. To achieve this, the scan chain routing method is first exploited to reduce the power consumption during scan-based testing through a cluster-based approach, which is compatible with the test compression architecture. Subsequently, a new test compression architecture is proposed to encode test patterns and enable the testing of each device-under-test (DUT) through a low input test pin count by using the unique properties of the proposed tri-state detector and boundary scan architecture. The experimental results show the decrease in the test I/O requirements and test power consumption. Based on these improvements, the test application time (TAT) was significantly reduced for ISCAS'89 and IWLS'05 OpenCores benchmark circuits compared to the previous methods, without a heavy burden on the additional H/W area and routing overhead.

中文翻译：

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先进的低引脚数测试架构可实现高效的多站点测试


随着半导体测试时间的迅速增加，目前的趋势是通过利用多站点测试来提高测试并行性。然而，由于测试仪I/O数量和电源容量有限，过多的测试I/O通道和测试功耗会导致多站点测试效率下降。在本文中，我们提出了一种先进的低引脚数测试架构，用于半导体中的高效多站点测试。为了实现这一目标，首先利用扫描链路由方法通过基于集群的方法来降低基于扫描的测试期间的功耗，该方法与测试压缩架构兼容。随后，提出了一种新的测试压缩架构来编码测试模式，并利用所提出的三态检测器和边界扫描架构的独特属性，通过低输入测试引脚数来测试每个被测设备（DUT） 。实验结果表明测试I/O要求和测试功耗都有所下降。基于这些改进，与之前的方法相比，ISCAS'89 和 IWLS'05 OpenCores 基准电路的测试应用时间 (TAT) 显着减少，且不会对额外的硬件面积和布线开销造成沉重负担。