This letter presents a distributed power amplifier (DPA) topology that improves both the power combining efficiency and the operation bandwidth. Multi-drive intra-stack coupling is introduced in the design of the gain cells to break the tradeoff between high output power (POUT) requirement and the achieved bandwidth. The proposed technique also compensates for the input transmission line (TL) loss to accommodate more stages and achieve flat gain and higher POUT. A prototype eightstage, 16-dB gain, 120-GHz bandwidth DPA is fabricated in 45-nm CMOS silicon-on-insulator (SOI) using elevated coplanar waveguide (CPW) TLs with a core area of 0.51 mm2. The amplifier maintains an output P1dB and PSAT higher than 18 and 20 dBm, respectively, up to 60 GHz and achieves a peak PAE of 19.7% at 15 GHz. A 64-quadrature-amplitude modulation (QAM) modulated signal with data rate 30 Gb/s (5 GBaud/s) is demonstrated at 55 GHz with a 13.5 dBm average POUT and 6.9% PAE while the error vector magnitude (EVM) is kept below 5%. To the authors' knowledge, the achieved 757-GHz gain-bandwidth product (GBW) is the highest among reported non-cascaded DPAs. The DPA has also the highest continuous-wave (CW) and modulated PAE compared to other reported distributed amplifiers (Das).

中文翻译：

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具有多驱动器堆栈内耦合的 120GHz 带宽 CMOS 分布式功率放大器


这封信提出了一种分布式功率放大器（DPA）拓扑，可提高功率组合效率和工作带宽。在增益单元的设计中引入了多驱动器堆栈内耦合，以打破高输出功率（POUT）要求和所实现的带宽之间的权衡。所提出的技术还可以补偿输入传输线 (TL) 损耗，以容纳更多级并实现平坦增益和更高的 POUT。原型八级、16dB 增益、120GHz 带宽 DPA 采用 45nm CMOS 绝缘体上硅 (SOI) 制造，使用核心面积为 0.51mm2 的高架共面波导 (CPW) TL。该放大器在高达 60 GHz 的频率下保持输出 P1dB 和 PSAT 分别高于 18 和 20 dBm，并在 15 GHz 时实现 19.7% 的峰值 PAE。在 55 GHz 下演示了数据速率为 30 Gb/s (5 GBaud/s) 的 64 正交幅度调制 (QAM) 调制信号，其平均 POUT 为 13.5 dBm，PAE 为 6.9%，同时误差矢量幅度 (EVM) 保持不变低于5%。据作者所知，所实现的 757 GHz 增益带宽积 (GBW) 是已报道的非级联 DPA 中最高的。与其他报道的分布式放大器 (Das) 相比，DPA 还具有最高的连续波 (CW) 和调制 PAE。