This paper proposes a three-stage coarse-fine-tuning analog-assisted digital low dropout regulator (AAD-LDO) without digital ripple. The digital regulation consists of two stages, which break the accuracy-speed-power trade-off. To further improve transient response, a step-variable counter used in the first stage is designed, which makes sure that the output current can track the load current rapidly. The ripple caused by the digital regulation disappears due to the existence of the analog-assistant stage (in the proposed AAD-LDO). As a result, the AAD-LDO achieves the output voltage with high accuracy. Designed in a 0.18μm CMOS process, the proposed AAD-LDO has a layout area of 0.133mm. For the input range of 1.2–1.8V, the output voltage is 1V. The maximum load current is 10mA at the input voltage of 1.2V. The linear regulation and load regulation are 0.061mV/V and 0.0082mV/mA, respectively. The over/undershoot is suppressed effectively for a 9.5mA load step. The peak current efficiency is 99.78%.

中文翻译：

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三级粗微调模拟辅助数字 LDO

本文提出了一种无数字纹波的三级粗微调模拟辅助数字低压差稳压器 (AAD-LDO)。数字调节由两个阶段组成，打破了精度-速度-功率的权衡。为了进一步提高瞬态响应，在第一级设计了一个步进变量计数器，确保输出电流能够快速跟踪负载电流。由于模拟辅助级的存在（在提议的 AAD-LDO 中），数字调节引起的纹波消失了。因此，AAD-LDO 实现了高精度的输出电压。设计在 0.18μm CMOS工艺，提出的AAD-LDO布局面积为0.133毫米。对于 1.2–1.8 的输入范围V，输出电压为1五、最大负载电流为10mA 在输入电压为 1.2五、线性调整率和负载调整率均为0.061mV/V 和 0.0082毫伏/毫安，分别。9.5 有效抑制过冲/下冲mA 负载阶跃。峰值电流效率为 99.78%。