This paper presents a 9-bit, 2-stage cyclic analog to digital converter (ADC) with a variable bias current control circuitry to reduce its power dissipation. Each stage outputs a three-bit digital word and the circuit requires four subcycles to perform a whole conversion. Since the accuracy required is higher in the first stage and first subcycle and decreases in subsequent cycles, the bias current of each operational transconductance amplifier is regulated depending on the subcycle of the conversion process. The resolution and sampling frequency of the converter make it suitable to be integrated with 8-bit CMOS imagers with column-parallel ADC architectures. The ADC has been designed using a 1.2 V 110 nm CMOS technology and the circuit consumes 27.9 µW at a sampling rate of 500 kS/s. At this sampling rate and at a 32 kHz input frequency, the circuit achieves 56 dB of SNDR and 9 bit ENOB. The Figure of Merit is 109 fJ/step.

本文提出了一种具有可变偏置电流控制电路以降低其功耗的9位2级循环模数转换器（ADC）。每个级输出一个三位数字字，电路需要四个子周期来执行整个转换。由于所需的精度在第一级和第一子周期中较高，而在随后的周期中降低，因此，根据转换过程的子周期来调节每个运算跨导放大器的偏置电流。该转换器的分辨率和采样频率使其适合与具有列并行ADC架构的8位CMOS成像器集成。ADC采用1.2 V 110 nm CMOS技术进行设计，该电路在500 kS / s的采样速率下消耗27.9 µW。在此采样率和32 kHz输入频率下，该电路可实现56 dB的SNDR和9位ENOB。品质因数为109 fJ /步。