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Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults
Journal of Electronic Testing ( IF 1.1 ) Pub Date : 2020-08-01 , DOI: 10.1007/s10836-020-05898-x
Shuo Cai , , Binyong He , Weizheng Wang , Peng Liu , Fei Yu , Lairong Yin , Bo Li

Radiation-induced single transient faults (STFs) are expected to evolve into multiple transient faults (MTFs) at nanoscale CMOS technology nodes. For this reason, the reliability evaluation of logic circuits in the presence of MTFs is becoming an important aspect of the design process of deep submicron and nanoscale systems. However, an accurate evaluation of the reliability of large-scale and very large-scale circuits is both very complex and time-consuming. Accordingly, this paper presents a novel soft error reliability calculation approach for logic circuits based on a probability distribution model. The correctness or incorrectness of individual logic elements are regarded as random events obeying Bernoulli distribution. Subsequently, logic element conversion-based fault simulation experiments are conducted to analyze the logical masking effects of the circuit when one logic element fails or when two elements fail simultaneously. On this basis, the reliability boundaries of the logic circuits can efficiently be calculated using the proposed probability model and fault simulation results. The proposed solution can obtain an accurate reliability range through single fault and double faults simulations with small sample sizes, and also scales well with the variation of the error rate of the circuit element. To validate the proposed approach, we have calculated the reliability boundaries of ISCAS’85, ISCAS’89, and ITC’99 benchmark circuits. Statistical analysis and experimental results demonstrate that our method is effective and scalable, while also maintaining sufficiently close accuracy.

中文翻译:

存在多个瞬态故障时纳米级逻辑电路的软错误可靠性评估

辐射引起的单一瞬态故障 (STF) 有望在纳米级 CMOS 技术节点上演变为多个瞬态故障 (MTF)。出于这个原因,在 MTF 存在下逻辑电路的可靠性评估正在成为深亚微米和纳米级系统设计过程的一个重要方面。然而,准确评估大规模和超大规模电路的可靠性既非常复杂又耗时。因此,本文提出了一种新的基于概率分布模型的逻辑电路软错误可靠性计算方法。单个逻辑元素的正确与否被视为服从伯努利分布的随机事件。随后,进行基于逻辑元件转换的故障仿真实验,分析当一个逻辑元件失效或两个元件同时失效时电路的逻辑掩蔽效应。在此基础上,可以使用所提出的概率模型和故障仿真结果有效地计算逻辑电路的可靠性边界。所提出的解决方案可以通过小样本量的单故障和双故障模拟获得准确的可靠性范围,并且可以很好地适应电路元件错误率的变化。为了验证所提出的方法,我们计算了 ISCAS'85、ISCAS'89 和 ITC'99 基准电路的可靠性边界。统计分析和实验结果表明,我们的方法是有效且可扩展的,
更新日期:2020-08-01
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