This paper presents a compact and robust opamp-free noise shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC). The proposed NS SAR ADC adopts extra one passive feed-forward path summing in realizing second-order noise shaping with the minimum modification to a standard SAR. Compared with previous works, the noise sources of residue sampling and first-order integration on filter capacitors are obviated. It implements 4\(\times\) passive gain by capacitive charge-pump techniques that compensates the partial loss of residue voltage and relaxes the specifications of comparator. According to the behavioral modeling and simulation results, an ENOB of 16.88-bit is achieved based on a 10-bit DAC array, at the OSR of 16. Through utilizing the Monte Carlo simulation, the proposed ADC architecture is proven to be a robust system.

本文提出了一种紧凑而强大的无运算放大器噪声整形（NS）逐次逼近寄存器（SAR）模数转换器（ADC）。提出的NS SAR ADC采用额外的一个无源前馈路径求和，以实现对二阶噪声整形，同时对标准SAR的修改最少。与以前的工作相比，消除了残留采样的噪声源和滤波电容器的一阶积分。它实现了4 \（\ times \）通过电容性电荷泵技术实现的无源增益，可补偿残留电压的部分损耗并放宽比较器的规格。根据行为建模和仿真结果，在OSR为16的情况下，基于10位DAC阵列，可实现16.88位的ENOB。通过使用蒙特卡洛仿真，所提出的ADC体系结构被证明是一种健壮的系统。