Purpose

The data protection is always a vital problem in the network era. High-speed cryptographic chip is an important part to ensure data security in information interaction. This paper aims to provide a new peripheral component interconnect express (PCIe) encryption card solution with high performance, high integration and low cost.

Design/methodology/approach

This work proposes a System on Chip architecture scheme of high-speed cryptographic chip for PCIe encryption card. It integrated CPU, direct memory access, the national and international cipher algorithm (data encryption standard/3 data encryption standard, Rivest–Shamir–Adleman, HASH, SM1, SM2, SM3, SM4, SM7), PCIe and other communication interfaces with advanced extensible interface-advanced high-performance bus three-level bus architecture.

Findings

This paper presents a high-speed cryptographic chip that integrates several high-speed parallel processing algorithm units. The test results of post-silicon sample shows that the high-speed cryptographic chip can achieve Gbps-level speed. That means only one single chip can fully meet the requirements of cryptographic operation performance for most cryptographic applications.

Practical implications

The typical application in this work is PCIe encryption card. Besides server’s applications, it can also be applied in terminal products such as high-definition video encryption, security gateway, secure routing, cloud terminal devices and industrial real-time monitoring system, which require high performance on data encryption.

Social implications

It can be well applied on many other fields such as power, banking, insurance, transportation and e-commerce.

Originality/value

Compared with the current strategy of high-speed encryption card, which mostly uses hardware field-programmable gate arrays or several low-speed algorithm chips through parallel processing in one printed circuit board, this work has provided a new PCIe encryption card solution with high performance, high integration and low cost only in one chip.

中文翻译：

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基于多种算法的外设互联快速加密卡片上系统设计与实现

目的

在网络时代，数据保护始终是一个至关重要的问题。高速密码芯片是保证信息交互中数据安全的重要组成部分。本文旨在提供一种新型的高性能、高集成度、低成本的PCIe加密卡解决方案。

设计/方法/方法

本文提出了一种用于PCIe加密卡的高速加密芯片的片上系统架构方案。它集成了CPU、直接内存访问、国内外密码算法（数据加密标准/3数据加密标准、Rivest–Shamir–Adleman、HASH、SM1、SM2、SM3、SM4、SM7）、PCIe等具有先进的通讯接口可扩展接口-高级高性能总线三级总线架构。

发现

本文介绍了一种集成了多个高速并行处理算法单元的高速密码芯片。后硅样品的测试结果表明，该高速密码芯片可以达到Gbps级别的速度。这意味着只需一颗芯片就可以完全满足大多数密码应用对密码操作性能的要求。

实际影响

在这项工作中的典型应用是 PCIe 加密卡。除服务器应用外，还可应用于高清视频加密、安全网关、安全路由、云终端设备、工业实时监控系统等对数据加密性能要求较高的终端产品。

社会影响

它可以很好地应用于电力、银行、保险、交通和电子商务等许多其他领域。

原创性/价值

与目前高速加密卡的策略多采用硬件现场可编程门阵列或多个低速算法芯片在一块印刷电路板上并行处理相比，这项工作提供了一种新的高性能PCIe加密卡解决方案。 , 高集成度和低成本只在一颗芯片上。