Mixed-signal components, such as low dropouts (LDOs) and phase locked loops (PLLs), are widely used inside the on-chip power management fabric of low power integrated system-on-chip (SoC) designs. The digital brain of the power management logic that is responsible for regulating the power delivery to different power domains in the chip has to consider the real time latencies of the analog components, which otherwise leads to functional errors in the domains being driven. The latencies may be viewed as contracts between the digital and the analog. This article presents an approach for generating assertions for protecting such mixed-signal latency contracts and using them to rule out timing bugs in the power management logic. Our tool flow enables the verification of the power management fabric, combining a novel mixed-signal assertion checking method in a simulation setting, and a full formal verification method for the digital brain of the power management logic. To the best of our knowledge, this is the first framework where assertions are used for binding analog latency contracts on the digital logic of power management.

中文翻译：

---

在电源管理中保护混合信号延迟合同的断言

混合信号组件，例如低压差 (LDO) 和锁相环 (PLL)，广泛用于低功耗集成片上系统 (SoC) 设计的片上电源管理结构中。负责调节芯片中不同电源域的功率传输的电源管理逻辑的数字大脑必须考虑模拟组件的实时延迟，否则会导致驱动域中的功能错误。延迟可以被视为数字和模拟之间的契约。本文介绍了一种生成断言以保护此类混合信号延迟合同并使用它们排除电源管理逻辑中的时序错误的方法。我们的工具流程可以验证电源管理结构，将模拟环境中的新型混合信号断言检查方法与电源管理逻辑的数字大脑的完整形式验证方法相结合。据我们所知，这是第一个使用断言将模拟延迟合同绑定到电源管理的数字逻辑上的框架。