A hybrid Miller-Cascode compensation (HMCC) scheme incorporating Miller compensation (MC) and cascode compensation on a nonsignal path (CCNSP) in the two-stage amplifiers is presented. The proposed HMCC resolves issues in other compensations such as CCNSP, cascode compensation on a signal path (CCSP), and hybrid cascode compensation (HCC) such that the gain peaking near unity gain frequency (UGF) in the open-loop transfer function is alleviated, which results in faster settling. To understand and validate the merit of the proposed HMCC, the locations of poles and a zero are analyzed through the small-signal model and compared with other compensations in terms of settling speed. Moreover, to verify the effect of gain peaking on settling speed, two pipeline ADCs employing HMCC and CCNSP are fabricated in a 0.11- $\mu \text{m}$ CMOS process. In measurement, the ADCs with HMCC achieve higher spurious-free dynamic range (SFDR) at the sampling frequencies above 20 MHz than the ADCs with CCNSP, which demonstrates that the proposed HMCC achieves faster settling than CCNSP due to gain peaking suppression.

中文翻译：

---

用于两级运算放大器快速建立的混合米勒-级联补偿

提出了一种混合米勒-级联补偿 (HMCC) 方案，该方案在两级放大器中的非信号路径 (CCNSP) 上结合了米勒补偿 (MC) 和级联补偿。提出的 HMCC 解决了其他补偿中的问题，例如 CCNSP、信号路径上的共源共栅补偿 (CCSP) 和混合共源共栅补偿 (HCC)，从而减轻了开环传递函数中接近单位增益频率 (UGF) 的增益峰值，这导致更快的稳定。为了理解和验证所提出的 HMCC 的优点，通过小信号模型分析了极点和零点的位置，并在稳定速度方面与其他补偿进行了比较。此外，为了验证增益峰值对稳定速度的影响，采用 HMCC 和 CCNSP 的两个流水线 ADC 在 0.11-$\mu\text{m}$ CMOS 工艺中制造。