This article presents two novel structures for designing current mode logic (CML) digital circuits [MOS CML (MCML) and multiple tail CML (MTCML)] in ultralow-power (ULP) and high-speed (HS) applications. The transistor’s bulk can be used as a digital signal input at a level, where it does not cause a disturbance to the operation of the transistor. Therefore, the number of transistors used in novel structures is reduced and it is possible to improve power delay product (PDP) and time propagation delay (TPD) in some of the tail currents. This technique is obtained through integrating the bulk-driven technique into the CML digital circuits, which are in the form of bulk-driven MCML (BD-MCML) and BD-MTCML. In the conventional CMOS technology, the proposed structures depend on the type of substrate. The BD-MCML structure uses a deep n-well technology and the BD-MTCML uses an n-well technology. The CML gates, such as AND, XOR, and D-latch, are suggested. The systematic use of the proposed structures is discussed in both HS and ULP applications. Finally, an unsigned multiplier is designed in the form of the BD-MTCML with a conventional 180-nm technology. Mixed-signal circuits are Serial/De-serial (SerDes), optical receivers, radio frequency (RF) receivers, and line drivers on the HS approach, and also video processors and A/D and D/A converters on the ULP approach.

中文翻译：

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PDP 和 TPD 适用于无线和有线应用的灵活 MCML 和 MTCML 超低功耗和高速结构

本文介绍了在超低功耗 (ULP) 和高速 (HS) 应用中设计电流模式逻辑 (CML) 数字电路 [MOS CML (MCML) 和多尾 CML (MTCML)] 的两种新颖结构。晶体管的块体可用作某一电平的数字信号输入，它不会对晶体管的操作造成干扰。因此，新结构中使用的晶体管数量减少，并且可以改善一些尾电流中的功率延迟积（PDP）和时间传播延迟（TPD）。该技术是通过将bulk-driven技术集成到CML数字电路中获得的，其形式有bulk-driven MCML（BD-MCML）和BD-MTCML。在传统的 CMOS 技术中，所提出的结构取决于衬底的类型。BD-MCML结构使用深n阱技术，BD-MTCML使用n阱技术。建议使用 CML 门，例如 AND、XOR 和 D-latch。在 HS 和 ULP 应用中讨论了所提议结构的系统使用。最后，采用传统的 180 纳米技术以 BD-MTCML 的形式设计了一个无符号乘法器。混合信号电路是串行/解串 (SerDes)、光接收器、射频 (RF) 接收器和 HS 方法中的线路驱动器，以及 ULP 方法中的视频处理器和 A/D 和 D/A 转换器。无符号乘法器以 BD-MTCML 的形式设计，采用传统的 180 纳米技术。混合信号电路是串行/解串 (SerDes)、光接收器、射频 (RF) 接收器和 HS 方法中的线路驱动器，以及 ULP 方法中的视频处理器和 A/D 和 D/A 转换器。无符号乘法器以 BD-MTCML 的形式设计，采用传统的 180 纳米技术。混合信号电路是串行/解串 (SerDes)、光接收器、射频 (RF) 接收器和 HS 方法中的线路驱动器，以及 ULP 方法中的视频处理器和 A/D 和 D/A 转换器。