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F-DNA: Fast Convolution Architecture for Deconvolutional Network Acceleration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems ( IF 2.8 ) Pub Date : 2020-07-02 , DOI: 10.1109/tvlsi.2020.3000519
Wendong Mao , Jun Lin , Zhongfeng Wang

Deconvolutional neural network (DeCNN), such as fully convolutional network (FCN) and generative adversarial network (GAN), has shown great potential in various vision tasks. Convolution and deconvolution, the two major operations of DeCNN, both require real-time hardware acceleration. However, some previous designs for deconvolutions require large memory for overlapped results, while others incur computation imbalance and cause resource underutilization. In this article, we propose an efficient method to convert deconvolutions to convolutions, which enables balanced computations to make full use of processing elements. Based on the fast FIR algorithm, a reconfigurable conv-deconv unit (RCU) with low complexity is designed, which can support various types of convolutions and deconvolutions. By exploiting the computing characteristics of RCUs, a computation-balance scheme is developed to eliminate large memory requirements caused by overlapped results. In addition, a fast convolution architecture for deconvolutional network acceleration (F-DNA) is proposed. The dataflow of F-DNA improves the computation efficiency through input data reuse. The architecture is implemented on Xilinx Virtex-UltraScale, for two typical DeCNNs, DCGAN and FSRCNN. Implementation results show that the proposed design outperforms existing works significantly, particularly in terms of computation efficiency and memory requirements.

中文翻译:


F-DNA:用于反卷积网络加速的快速卷积架构



反卷积神经网络(DeCNN),如全卷积网络(FCN)和生成对抗网络(GAN),在各种视觉任务中表现出了巨大的潜力。卷积和反卷积是DeCNN的两大运算,都需要实时硬件加速。然而,之前的一些反卷积设计需要大量内存来存储重叠结果,而另一些则会导致计算不平衡并导致资源利用不足。在本文中,我们提出了一种将反卷积转换为卷积的有效方法,使平衡计算能够充分利用处理元素。基于快速FIR算法,设计了一种低复杂度的可重构的卷积-反卷积单元(RCU),可以支持各种类型的卷积和反卷积。通过利用 RCU 的计算特性,开发了一种计算平衡方案,以消除由于重叠结果而导致的大量内存需求。此外,还提出了一种用于反卷积网络加速(F-DNA)的快速卷积架构。 F-DNA的数据流通过输入数据重用提高了计算效率。该架构在 Xilinx Virtex-UltraScale 上实现,适用于两种典型的 DeCNN:DCGAN 和 FSRCNN。实现结果表明,所提出的设计显着优于现有的工作,特别是在计算效率和内存需求方面。
更新日期:2020-07-02
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