Due to the rapid advance of integrated circuit (IC)-related technologies, design complexity is dramatically increasing in printed circuit boards (PCBs). Nowadays, a dense PCB contains thousands of pin shapes and signal nets, and such a huge net count makes the manual design of PCBs an extremely time-consuming task, especially in the routing phase. Bus routing, which consists of assigning all the buses to routing layers and topologically routing them on each layer while satisfying some constraints, is one of the most difficult steps in PCB routing. In addition, to take timing into consideration, all bits of a bus are highly preferred to have approximately the same length which are referred to as the length-matching issue. In advanced technology nodes, moreover, routing tracks are provided to help router adhere to design rules and help mask coloring. In this article, we develop a sophisticated bus router which optimizes routability, wirelength, as well as length-matching while simultaneously considering track resources, obstacles, and other design constraints. Experimental results show that the proposed algorithm flow can outperform the state-of-the-art bus routers in terms of the total routing cost and the min–max length difference for the benchmarks provided by the 2018 CAD contest at ICCAD.

中文翻译：

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考虑非均匀轨道资源的避障长度匹配总线路由

由于集成电路 (IC) 相关技术的快速发展，印刷电路板 (PCB) 的设计复杂性急剧增加。如今，一块密集的PCB包含数以千计的引脚形状和信号网络，如此庞大的网络数量使得PCB的手动设计成为一项极其耗时的任务，尤其是在布线阶段。总线布线包括将所有总线分配到布线层并在满足某些约束的同时在每一层上对它们进行拓扑布线，是 PCB 布线中最困难的步骤之一。此外，为了考虑时序，总线的所有位都非常优选具有大致相同的长度，这被称为长度匹配问题。此外，在先进技术节点中，提供布线轨道以帮助布线器遵守设计规则并帮助遮罩着色。在本文中，我们开发了一个复杂的总线路由器，它优化了可布线性、线长以及长度匹配，同时考虑了轨道资源、障碍物和其他设计约束。实验结果表明，对于 ICCAD 2018 年 CAD 竞赛提供的基准，所提出的算法流程在总路由成本和最小-最大长度差异方面可以优于最先进的总线路由器。