当前位置: X-MOL 学术IEEE Trans. Consum. Electron. › 论文详情
Our official English website, www.x-mol.net, welcomes your feedback! (Note: you will need to create a separate account there.)
Hardware-Efficient 2D-DCT/IDCT Architecture for Portable HEVC-Compliant Devices
IEEE Transactions on Consumer Electronics ( IF 4.3 ) Pub Date : 2020-08-01 , DOI: 10.1109/tce.2020.3006213
Ashish Singhadia , Meghan Mamillapalli , Indrajit Chakrabarti

Low power hardware acceleration cores for integration into real-time High Efficiency Video Coding (HEVC) codec for smartphones, tablets, camcorders, and televisions are in great demand. This need motivates one for an efficient realization of Discrete Cosine Transform (DCT) and Inverse-DCT (IDCT) for HEVC. This paper presents an algorithm to calculate the required minimum number of low-frequency DCT-output/IDCT-input coefficients for 4, 8, 16, and 32-point DCT/IDCT in HEVC, such that there is a slight decrease in peak-signal-to-noise-ratio (<0.15 decibel) and a minor increment in bitrate (<1.5%) as compared to the reference HEVC-Test-Model (HM) Software. However, the encoding time gets reduced at most by 17.95% for Class-A type sequences, while reporting mean-squared-error and structural-similarity of 1.42 and 0.9913, respectively for 4K ultra-high-definition videos. Moreover, HEVC-compliant computationally efficient architectures are introduced for n-point DCT/IDCT. The presented flexible Transpose Memory architecture uses only sixteen random-access-memories to support all transform-unit sizes in HEVC. The proposed two-dimensional DCT/IDCT architecture can process up to 288@ $4K$ frames-per-second, and it consumes the minimum power, energy, and area of 11.23 milliwatts, 2.34 picojoules, and 120 kilo-gate-equivalents, respectively. Such design with low power, area, and energy features can be included in a real-time HEVC codec for HEVC-compliant consumer electronic devices.

中文翻译:

适用于便携式 HEVC 兼容设备的硬件高效 2D-DCT/IDCT 架构

用于集成到智能手机、平板电脑、摄像机和电视的实时高效视频编码 (HEVC) 编解码器的低功耗硬件加速内核需求量很大。这种需求促使人们有效地实现 HEVC 的离散余弦变换 (DCT) 和逆 DCT (IDCT)。本文提出了一种算法来计算 HEVC 中 4、8、16 和 32 点 DCT/IDCT 所需的低频 DCT 输出/IDCT 输入系数的最小数量,从而使峰值-与参考 HEVC 测试模型 (HM) 软件相比,信噪比 (<0.15 分贝) 和比特率的微小增量 (<1.5%)。然而,A 类序列的编码时间最多减少 17.95%,同时报告均方误差和结构相似度分别为 1.42 和 0.9913,分别用于4K超高清视频。此外,为 n 点 DCT/IDCT 引入了符合 HEVC 的计算高效架构。提出的灵活转置内存架构仅使用 16 个随机访问内存来支持 HEVC 中的所有变换单元大小。所提出的二维 DCT/IDCT 架构每秒可处理高达 288@$4K$ 帧,并且它消耗的功率、能量和面积最小,为 11.23 毫瓦、2.34 皮焦和 120 千克门当量,分别。这种具有低功率、面积和能量特性的设计可以包含在符合 HEVC 的消费电子设备的实时 HEVC 编解码器中。提出的灵活转置内存架构仅使用 16 个随机访问内存来支持 HEVC 中的所有变换单元大小。所提出的二维 DCT/IDCT 架构每秒可处理高达 288@$4K$ 帧,并且它消耗的功率、能量和面积最小,为 11.23 毫瓦、2.34 皮焦和 120 千克门当量,分别。这种具有低功率、面积和能量特性的设计可以包含在符合 HEVC 的消费电子设备的实时 HEVC 编解码器中。提出的灵活转置内存架构仅使用 16 个随机访问内存来支持 HEVC 中的所有变换单元大小。所提出的二维 DCT/IDCT 架构每秒可处理高达 288@$4K$ 帧,并且它消耗的功率、能量和面积最小,为 11.23 毫瓦、2.34 皮焦和 120 千克门当量,分别。这种具有低功率、面积和能量特性的设计可以包含在符合 HEVC 的消费电子设备的实时 HEVC 编解码器中。
更新日期:2020-08-01
down
wechat
bug