Intellectual property (IP) core of digital signal processing (DSP) kernels act as hardware accelerators in consumer electronics (CE) systems. However due to rising threats of cloning and counterfeiting to an IP core, security remains an important subject of research for these hardware accelerators. This paper presents a novel key-driven hash-chaining based hardware steganography for securing such IP cores used in CE systems. The proposed approach is capable to implant secret invisible stego-marks in design using hash-chaining process that incorporates switches, strong large stego-keys, multiple encoding algorithms and hash blocks. The methodology proposed provides massive security against IP cloning and counterfeiting while incurring nominal design overhead (<; 0.3 %). The results of the proposed approach on comparison with state of the art indicated significantly stronger digital evidence (lower probability of co-incidence), stronger key size (in bits) and lower design cost using proposed stego-marks. Further, from an attacker's perspective, the proposed steganography increases an attacker's effort manifold during decoding the valid stego-key value (for generating/extracting original secret stego-mark), compared to existing approaches.

中文翻译：

---

IP 核隐写术使用基于开关的密钥驱动哈希链和编码来保护 CE 系统中使用的 DSP 内核


数字信号处理 (DSP) 内核的知识产权 (IP) 内核充当消费电子 (CE) 系统中的硬件加速器。然而，由于 IP 核的克隆和伪造威胁不断增加，安全性仍然是这些硬件加速器研究的重要课题。本文提出了一种新颖的基于密钥驱动的哈希链的硬件隐写术，用于保护 CE 系统中使用的此类 IP 核。所提出的方法能够使用哈希链接过程在设计中植入秘密的隐形隐写标记，该过程结合了开关、强大的大型隐写密钥、多种编码算法和散列块。所提出的方法提供了针对 IP 克隆和伪造的强大安全性，同时产生了名义设计开销 (<；0.3 %)。所提出的方法与现有技术相比的结果表明，使用所提出的隐写标记具有明显更强的数字证据（较低的重合概率）、更强的密钥大小（以位为单位）和更低的设计成本。此外，从攻击者的角度来看，与现有方法相比，所提出的隐写术在解码有效隐写密钥值（用于生成/提取原始秘密隐写标记）期间增加了攻击者的工作量。