In this work, the high-performance junctionless-mode (JL) and low-power inversion-mode (IM) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with nanosheet channels (less than 10-nm in thickness) are vertically integrated in monolithic three-dimensional integrated circuit (3D-IC) structure. Both JL and IM TFTs can exhibit high on/off current ratio over 107 to demonstrate their performance. The JL TFT has much higher on-state current ~ 24 times than it of the IM TFT. And the IM-TFT has much lower SS ~ 0.104 V/decade and off-current ~ 0.04 times than them of the JL TFT. However, the fabrication of the top-devices (JL TFTs) would degrade the performance of underlying-devices (IM TFTs), resulting in the threshold voltage shift of the IM TFTs from 0.61 to 2.17 V, SS increase from 0.104 to 0.218 V/decade and on-state current degradation from 16 to 3 mA. In order to further understand the reasons, the IM TFT with top-device removal process is also fabricated, which exhibits a partial recovery in performance. The results indicate the presence and fabrication process of the top-device would lead to the defect generation in the underlying-device. The results provide a new consideration for monolithic 3D-IC manufacturing technology.

中文翻译：

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垂直堆叠单片 3D-IC 工艺对底层薄膜晶体管特性的影响

在这项工作中，高性能无结模式 (JL) 和低功率反转模式 (IM) 多晶硅 (poly-Si) 薄膜晶体管 (TFT) 具有纳米片通道（厚度小于 10 纳米） ) 垂直集成在单片三维集成电路 (3D-IC) 结构中。JL 和 IM TFT 都可以表现出超过 107 的高开/关电流比，以证明它们的性能。JL TFT 的导通电流比 IM TFT 高得多~24 倍。IM-TFT 的 SS ~ 0.104 V/decade 和关断电流比 JL TFT 低 ~ 0.04 倍。然而，顶部器件（JL TFT）的制造会降低底层器件（IM TFT）的性能，导致 IM TFT 的阈值电压从 0.61 V 漂移到 2.17 V，SS 从 0.104 增加到 0。218 V/decade 和通态电流衰减从 16 到 3 mA。为了进一步了解原因，还制作了顶部器件去除工艺的 IM TFT，其表现出部分性能恢复。结果表明顶部器件的存在和制造过程会导致底层器件中的缺陷产生。该结果为单片 3D-IC 制造技术提供了新的考虑。