Abstract Integrated circuits (ICs) employ static and dynamic logic to improve performance and scalability. This paper presents a new circuit design approach named pseudo-dynamic logic (PDL), which shows the advantages of both static and dynamic cells. The PDL is evaluated by using a new full adder cell with 18 transistors. In the presented full adder, gate diffusion input (GDI), transmission gate (TG), and float techniques are combined, and pull-up or pull-down networks are changed into a new configuration so that the number of transistors and internal nodes will decrease. Post-layout simulations and digital image addition are performed to evaluate the real environment and practical application of the cell. Peak signal to noise ratio (PSNR), mean square error (MSE), and structural similarity index metric (SSIM) are calculated to study the cell performance in image processing. Compared to the dynamic and static circuits, the proposed PDL-based full adder cell performs better, and the results validate its effectiveness.

中文翻译：

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一种用于图像相加的低功耗伪动态全加器单元

摘要 集成电路 (IC) 采用静态和动态逻辑来提高性能和可扩展性。本文提出了一种称为伪动态逻辑 (PDL) 的新电路设计方法，它展示了静态和动态单元的优点。PDL 是通过使用具有 18 个晶体管的新全加器单元来评估的。在提出的全加器中，门扩散输入 (GDI)、传输门 (TG) 和浮动技术相结合，并将上拉或下拉网络更改为新的配置，以便晶体管和内部节点的数量将减少。执行布局后模拟和数字图像添加以评估单元的真实环境和实际应用。峰值信噪比 (PSNR)、均方误差 (MSE)、计算结构相似性指标（SSIM）以研究细胞在图像处理中的性能。与动态和静态电路相比，所提出的基于 PDL 的全加器单元性能更好，结果验证了其有效性。