Sigma-delta (SD) modulator based DACs are simple circuits with low accuracy requirements in their analog components. However, their signal bandwidth is limited by speed constrains. In this respect, Time-Interleaving (TI) allows the designer to trade-off between complexity and speed by replacing the original architecture by N parallel paths clocked at a frequency N times smaller. Unfortunately, this is only possible for small values of N because the resulting TI architecture has long combinatorial paths. These paths reduce the maximum clock rate. In closed-loop SD architectures these paths cannot be broken by the insertion of registers, because an increase of the loop delay compromises the stability of the modulator. This paper proposes a TI decomposition in open-loop SD modulators, which allows the insertion of as many registers as desired to shorten the critical combinatorial path. Consequently, the clock frequency (and, hence, the performances) can be increased at its maximum. The proposed method is illustrated with a second-order modulator, which has been synthesized in an FPGA (Spartan-6 xc6slx75t). Post-route static timing analysis and simulations show a considerable increase of performances. In authorś knowledge, it is the first time that TI is applied in open-loop SD modulators, resulting in very speed DACs.

基于Sigma-Delta（SD）调制器的DAC是简单电路，其模拟组件的精度要求较低。但是，它们的信号带宽受到速度限制的限制。在这方面，时间交织（TI）允许设计人员通过以时钟频率N倍的N条并行路径代替原始架构，从而在复杂度和速度之间进行权衡。不幸的是，这仅适用于较小的N值因为生成的TI架构具有很长的组合路径。这些路径会降低最大时钟速率。在闭环SD体系结构中，这些路径不能通过插入寄存器来中断，因为环路延迟的增加会损害调制器的稳定性。本文提出了开环SD调制器中的TI分解方法，该方法可以插入所需的任意数量的寄存器，以缩短关键的组合路径。因此，可以最大程度地提高时钟频率（从而提高性能）。用二阶调制器说明了该方法，该调制器已在FPGA（Spartan-6 xc6slx75t）中进行了合成。路由后静态时序分析和仿真显示了性能的显着提高。就作者而言，