To reduce specific on-resistance (R_on,sp) of power devices, a novel SOI (silicon-on-insulator) trench gate LDMOS with heavily doping L-shaped P/N pillars and vertical dual-trench-gates is proposed in this paper, and its physical mechanism and electrical performance are investigated by numerical simulation. The L-shaped P-pillar raises the optimal doping impurity concentration of the drift region (N_d) remarkably from 1.7 × 10¹⁵ cm⁻³ to 1.25 × 10¹⁶ cm⁻³ by causing assistant depletion effect for drift region, hence a lower specific on-resistance (R_on,sp) with a 3.6 mΩ·cm² is achieved. Meanwhile, the voltage capacity of the new structure is improved resulting from two new electric-field peaks produced by L-shaped P/N pillars. Consequently, a much lower R_on,sp and a higher breakdown voltage (BV) are achieved by the proposed structure. Simulated results show that the R_on,sp, BV, and Baliga’s figure of merit (FOM, FOM = BV²/R_on,sp) for the new structure are improved by 84.3%, 31.4%, and 991%, respectively, in comparison with the conventional trench LDMOS.

为了降低功率器件的比导通电阻（R _on，sp），提出了一种新颖的SOI（绝缘体上硅）沟槽栅极LDMOS，该栅极具有重掺杂L形P / N柱和垂直双沟槽栅极通过数值模拟研究了其物理机理和电性能。L形P柱通过对漂移区产生辅助耗尽效应，将漂移区的最佳掺杂杂质浓度（N _d）从1.7×10 ¹⁵  cm ^-3显着提高到1.25×10 ¹⁶  cm ^-3，因此降低了比导通电阻（R _on，sp）为3.6mΩ·cm ²已完成。同时，由于L形P / N柱产生了两个新的电场峰值，因此提高了新结构的电压容量。因此，所提出的结构实现了低得多的R _on，sp和更高的击穿电压（BV）。模拟结果表明，新结构的R _on，sp，BV和Baliga的品质因数（FOM，FOM = BV ² / R _on，sp）分别提高了84.3％，31.4％和991％。与常规沟槽LDMOS的比较。