We identify an optimum channel length for planar Laterally Diffused Metal-Oxide-Semiconductor (LDMOS) field-effect transistors, in terms of the specific on-resistance, through systematic device simulation and optimization. We simulate LDMOS devices with different channel lengths ranging from 100 nm to 10 nm, modifying the length of the drift region and doping concentration of the body region to match a pre-determined leakage current suitable for low-voltage power applications (3.3V and 5V). For devices with a channel length exceeding 40 nm, reducing the channel length decreases the on-resistance as expected. Below 40 nm, an increase in resistance is observed as the result of an increased body doping concentration leading to significant electron mobility degradation in the channel area.

中文翻译：

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用于低压电源应用的平面 LDMOS 场效应晶体管的沟道长度优化

我们通过系统的器件模拟和优化，根据特定导通电阻确定了平面横向扩散金属氧化物半导体 (LDMOS) 场效应晶体管的最佳沟道长度。我们模拟具有 100 nm 至 10 nm 不同沟道长度的 LDMOS 器件，修改漂移区的长度和体区的掺杂浓度，以匹配适用于低压电源应用（3.3V 和 5V）的预定漏电流）。对于沟道长度超过 40 nm 的器件，减少沟道长度会降低导通电阻。低于 40 nm，观察到电阻增加，这是由于体掺杂浓度增加导致沟道区域中电子迁移率显着降低的结​​果。