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A New Sub-1 Volt 17ppm/°C Offset-Insensitive Resistorless Switched-capacitor Bandgap Voltage Reference
Journal of Circuits, Systems and Computers ( IF 0.9 ) Pub Date : 2020-05-12 , DOI: 10.1142/s0218126621500298
Emad Ebrahimi 1 , Maliheh Arabnasery 1
Affiliation  

A new PVT compensated voltage reference is presented by using switched-capacitor (S.C.) technique. In the proposed bandgap voltage reference (BGR), a p–n junction is biased with different currents during two different phases and required PTAT and CTAT voltages generated and held by two capacitors. Using a capacitive voltage divider, the PTAT voltage is weighted such that the sub-1V bandgap voltage is achievable. In order to cancel the effect of op-amp offset and to relax the design of op-amp, the offset voltage of the op-amp is sampled by a capacitor during a specified phase and inversely is added to the final bandgap voltage in next phase. The analysis of the proposed S.C. BGR is supplemented by simulation of a 0.5-V BGR with 28[Formula: see text][Formula: see text][Formula: see text]W power consumption in a standard 0.18[Formula: see text][Formula: see text][Formula: see text]m CMOS technology. Simulation results show that the average temperature coefficient of the S.C. BGR is 17[Formula: see text]ppm/C and it is robust against the process variations. Applying an arbitrary 100-mV op-amp offset results in a lower than 1.1[Formula: see text]mV deviation in generated reference voltage. Due to the better matching of MIM capacitors in CMOS process (rather than resistors used in conventional BGR) the proposed S.C. bandgap provides good accuracy without any post trimming. Monte–Carlo analysis shows that [Formula: see text]/[Formula: see text] of the generated reference voltage is as low as 0.7%. The sensitivity of the proposed BGR to supply variation is also less than 1%/V.

中文翻译:

一种新的低于 1 伏的 17ppm/°C 失调不敏感无电阻开关电容器带隙电压基准

采用开关电容(SC)技术提出了一种新的 PVT 补偿电压基准。在建议的带隙电压基准 (BGR) 中,ap-n 结在两个不同的阶段被不同的电流偏置,并且需要由两个电容器产生和保持的 PTAT 和 CTAT 电压。使用电容分压器,对 PTAT 电压进行加权,从而可以实现低于 1V 的带隙电压。为了消除运放失调的影响,放宽运放的设计,运放的失调电压在指定阶段由一个电容采样,并在下一阶段反相加到最终的带隙电压上. 对提议的 SC BGR 的分析通过 28 [公式:见文本][公式:见文本][公式:见文本]标准 0.18 [公式:见正文][公式:见正文][公式:见正文]m CMOS技术。仿真结果表明,SC BGR的平均温度系数为17[公式:见正文]ppm/C 并且它对过程变化具有鲁棒性。应用任意 100-mV 运算放大器偏移会导致生成的参考电压的偏差低于 1.1[公式:见正文]mV。由于 CMOS 工艺中的 MIM 电容器(而不是传统 BGR 中使用的电阻器)具有更好的匹配性,所提出的 SC 带隙提供了良好的精度,而无需任何后修整。蒙特卡洛分析表明[公式:见正文]/[公式:见正文]产生的参考电压低至0.7%。提议的 BGR 对电源变化的敏感性也低于 1%/V。
更新日期:2020-05-12
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