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Observing the Invisible: Live Cache Inspection for High-Performance Embedded Systems
arXiv - CS - Other Computer Science Pub Date : 2020-07-23 , DOI: arxiv-2007.12271
Dharmesh Tarapore, Shahin Roozkhosh, Steven Brzozowski, Renato Mancuso

The vast majority of high-performance embedded systems implement multi-level CPU cache hierarchies. But the exact behavior of these CPU caches has historically been opaque to system designers. Absent expensive hardware debuggers, an understanding of cache makeup remains tenuous at best. This enduring opacity further obscures the complex interplay among applications and OS-level components, particularly as they compete for the allocation of cache resources. Notwithstanding the relegation of cache comprehension to proxies such as static cache analysis, performance counter-based profiling, and cache hierarchy simulations, the underpinnings of cache structure and evolution continue to elude software-centric solutions. In this paper, we explore a novel method of studying cache contents and their evolution via snapshotting. Our method complements extant approaches for cache profiling to better formulate, validate, and refine hypotheses on the behavior of modern caches. We leverage cache introspection interfaces provided by vendors to perform live cache inspections without the need for external hardware. We present CacheFlow, a proof-of-concept Linux kernel module which snapshots cache contents on an NVIDIA Tegra TX1 SoC (system on chip).

中文翻译:

观察不可见:高性能嵌入式系统的实时缓存检查

绝大多数高性能嵌入式系统都实现了多级 CPU 缓存层次结构。但是这些 CPU 缓存的确切行为历来对系统设计人员来说是不透明的。如果没有昂贵的硬件调试器,对缓存构成的理解充其量仍然是微不足道的。这种持久的不透明度进一步模糊了应用程序和操作系统级组件之间复杂的相互作用,尤其是当它们竞争缓存资源的分配时。尽管缓存理解被降级为静态缓存分析、基于性能计数器的分析和缓存层次结构模拟等代理,但缓存结构和演变的基础继续避开以软件为中心的解决方案。在本文中,我们探索了一种通过快照研究缓存内容及其演变的新方法。我们的方法补充了现有的缓存分析方法,以更好地制定、验证和完善关于现代缓存行为的假设。我们利用供应商提供的缓存内省接口来执行实时缓存检查,而无需外部硬件。我们展示了 CacheFlow,这是一个概念验证 Linux 内核模块,它在 NVIDIA Tegra TX1 SoC(片上系统)上对缓存内容进行快照。
更新日期:2020-07-27
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