When digital circuits are designed, it is generally accepted that the circuit delay will rise by reducing supply voltage and increasing temperature. It is well known that this presumption breaks when the supply voltage is low and the delay decrease with rise in temperature. This is due to the mutual compensation of physical parameters that change with temperature. This phenomenon is known as inverse temperature dependence (ITD) and the supply voltage at which this occur is known as Temperature Inversion Voltage (TIV) or crossover voltage. In this paper, an $\alpha$-power law based unified (valid in all inversion/saturation regions) analytical MOSFET model is utilized to study the phenomenon of ITD for basic digital building blocks in order to have first hand estimation of TIV up to 22 nm technology node. The results obtained are verified with industry standard BSIM3v3 up to 100 nm and BSIM4 below 100 nm.

设计数字电路时，通常公认的是，通过降低电源电压和提高温度，电路延迟会增加。众所周知，当电源电压低时该推定会中断，并且延迟会随着温度的升高而减小。这是由于相互补偿随温度变化的物理参数。这种现象称为反向温度依赖性（ITD），发生这种情况的电源电压称为温度反向电压（TIV）或交叉电压。在本文中，$\alpha$基于功率法的统一（在所有反演/饱和区均有效）分析型MOSFET模型用于研究基本数字构件的ITD现象，以便第一手估算TIV高达22 nm技术节点。使用高达100 nm的行业标准BSIM3v3和低于100 nm的BSIM4验证了获得的结果。