The two-dimensional Gaussian smoothing filter (2D-GSF) is one of the most useful techniques in image processing. Since the 2D-GSF requires high computational resources, its efficient design and implementation are critical in real-time processing purposes. Approximate computing is a new method that can be used to increase the performance of 2D Gaussian filter design with low computing overhead on field-programmable gate arrays (FPGAs). This study aims to provide a low-latency Gaussian filter architecture on FPGA such that it can be used in real-time processing applications. In this regard, accurate and approximate carry-save adders (CSAs) have been used in adder tree-based Gaussian filters. In our proposed method, we use two approximation steps: in the first step, we use an approximation structure named Speed–Power–Area–Accuracy for Gaussian filter design and in the second stage, we use approximate CSAs to convert adder-tree structures that are used in Gaussian filter, and as a result, we have significantly reduced the delay. The results of simulation and implementation show that the latency has reduced in a 3[Formula: see text] 3 2D-GSF architecture up to 22% using proposed accurate CSAs and 45% using proposed approximate CSAs, compared to existing Gaussian filters with an adder tree structure.

中文翻译：

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使用近似进位保存加法器的低延迟二维高斯平滑滤波器的有效实现

二维高斯平滑滤波器 (2D-GSF) 是图像处理中最有用的技术之一。由于 2D-GSF 需要大量计算资源，因此其高效设计和实施对于实时处理目的至关重要。近似计算是一种新方法，可用于在现场可编程门阵列 (FPGA) 上以低计算开销提高二维高斯滤波器设计的性能。本研究旨在提供一种基于 FPGA 的低延迟高斯滤波器架构，使其可用于实时处理应用。在这方面，精确和近似的进位保存加法器 (CSA) 已用于基于加法器树的高斯滤波器。在我们提出的方法中，我们使用两个近似步骤：在第一步中，我们使用名为 Speed-Power-Area-Accuracy 的近似结构进行高斯滤波器设计，在第二阶段，我们使用近似 CSA 来转换高斯滤波器中使用的加法器树结构，结果，我们显着降低了延迟。仿真和实现的结果表明，与现有的带有加法器的高斯滤波器相比，使用提议的准确 CSA 和使用提议的近似 CSA 的 3 2D-GSF 架构的延迟减少了 22% 和 45%。树状结构。