Multiple-input multiple-output (MIMO) Minimum mean-square error (MMSE) receivers are widely adopted in the latest communication standards and reducing the complexity of these receivers while preserving the error performance is highly desirable. In this work, we study the error performance and implementation complexity of MIMO MMSE receivers when combined with a coordinate interleaved signal space diversity (SSD) technique. Contrary to the well-known trade-off between the error performance and implementation complexity, the proposed system leads to a considerably simplified MIMO MMSE receiver with significant performance gains when compared to the original MIMO MMSE receiver. Unlike the standard MIMO MMSE receiver, the proposed coordinate interleaved technique induces a block diagonal transmit correlation matrix providing both performance enhancement and complexity reduction. The results show that the error performance can be improved more than 10[Formula: see text]dB with up to 71% computational complexity reduction. The complexity comparison between the original and proposed approaches is also verified by means of field-programmable gate array (FPGA) implementation.

中文翻译：

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通过坐标交织增强性能的低复杂度 MIMO MMSE 接收器

多输入多输出 (MIMO) 最小均方误差 (MMSE) 接收器在最新的通信标准中被广泛采用，并且在保持错误性能的同时降低这些接收器的复杂性是非常可取的。在这项工作中，我们研究了 MIMO MMSE 接收器与坐标交错信号空间分集 (SSD) 技术相结合时的错误性能和实现复杂性。与众所周知的错误性能和实现复杂性之间的权衡相反，与原始 MIMO MMSE 接收器相比，所提出的系统导致显着简化的 MIMO MMSE 接收器具有显着的性能增益。不同于标准的 MIMO MMSE 接收器，所提出的坐标交错技术引入了一个块对角发射相关矩阵，提供了性能增强和复杂性降低。结果表明，误差性能可以提高 10[公式：见正文]dB 以上，计算复杂度降低高达 71%。原始方法和提议方法之间的复杂性比较也通过现场可编程门阵列 (FPGA) 实现进行了验证。