As the size of metal–oxide semiconductor field-effect transistors (MOSFETs) is shrinking, there are new challenges at different stages of very-large-scale integration (VLSI) design flow. Several devices are densely placed compared to the older counterparts. 3-D integrated chip (3-D IC) packaging is one of the famous packaging technologies where in IC contains multiple dies having various modules or subsystems interconnected through silicon via TSVs. One of the major challenges in 3-D IC packaging is thermal management. This article proposes a descending order thermal distribution (DOTD) partitioning algorithm that helps to improve heat sinking in flip-chip based 3-D ICs along with reducing the number of TSVs. The proposed algorithm is run on thermal benchmark circuits from VLSI Computer-Aided Design (CAD) Lab of the University of California and results are compared with different partitioning algorithms. It shows that the proposed partitioning algorithm gives better thermal distribution facilitating improved heat sinking in 3-D ICs along with up to 14.54% reduction in TSV.

中文翻译：

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倒装芯片封装的3D IC降序热分布划分算法，以提高散热效果并减少TSV数量

随着金属氧化物半导体场效应晶体管（MOSFET）的尺寸缩小，在超大规模集成（VLSI）设计流程的不同阶段面临着新的挑战。与较旧的设备相比，有几台设备密集放置。3-D集成芯片（3-D IC）封装是著名的封装技术之一，其中IC包含多个管芯，这些管芯具有通过TSV通过硅互连的各种模块或子系统。3D IC封装的主要挑战之一是热管理。本文提出了一种降序热分布（DOTD）分区算法，该算法有助于改善基于倒装芯片的3-D IC中的散热，并减少TSV的数量。该算法在加州大学VLSI计算机辅助设计（CAD）实验室的热基准电路上运行，并将结果与​​不同的分区算法进行了比较。结果表明，所提出的分区算法可提供更好的热分布，从而有助于改善3-D IC中的散热，并降低了TSV达14.54％。