Designing a high-quality switch block ensures the efficient data transmission in digital circuits and systems. In this paper, an innovative 2:1 multiplexer is successfully designed based on the previously proposed side-contacted field-effect diodes (S-FEDs) at 180 nm SOI technology node. Optimization of the reservoir thickness and gate work function of the S-FED satisfy high I_ON/I_OFF ratio and noise-immunity. DC, AC, and transient mixed-mode simulations are employed to scrutinize and compare performance of constituent logic gates based on the S-FED and CMOS. Simulation results demonstrate superior noise margins up to 100 mV for the S-FED-based inverter compared with the CMOS-based counterpart. Furthermore, the S-FED-based transmission gate with switching frequency of 38.9 GHz can act as a high-speed alternative for the CMOS-based one. Both multiplexer architectures configured by the S-FED and CMOS are compared in terms of performance parameters. In this regard, average power consumption and PDP quantities for the S-FED-based multiplexer reveal significant reductions by about 2 and 3 orders of magnitude, respectively, compared with the CMOS-based one. In addition, propagation delay time increases drastically with scaling power supply in the CMOS-based multiplexer; while, this increase is suppressed for the S-FED-based version.

设计高质量的开关模块可确保在数字电路和系统中进行有效的数据传输。在本文中，基于先前提出的180 nm SOI技术节点上的侧接触场效应二极管（S-FED），成功设计了一种创新的2：1多路复用器。S-FED的储层厚度和闸门功函数的优化满足高I _ON / I _OFF比和抗噪能力。直流，交流和瞬态混合模式仿真用于检查和比较基于S-FED和CMOS的组成逻辑门的性能。仿真结果表明，与基于CMOS的逆变器相比，基于S-FED的逆变器具有高达100 mV的卓越噪声容限。此外，开关频率为38.9 GHz的基于S-FED的传输门可以充当基于CMOS的传输门的高速替代品。比较了S-FED和CMOS配置的两种多路复用器体系结构的性能参数。在这方面，与基于CMOS的多路复用器相比，基于S-FED的多路复用器的平均功耗和PDP量分别显着降低了约2个和3个数量级。此外，随着基于CMOS的多路复用器中电源的缩放，传播延迟时间急剧增加。同时，对于基于S-FED的版本，此增加受到抑制。