This paper presents an efficient, cost effective design implementation of a hybrid digital architecture for space vector pulse width modulation (SVPWM) method for multilevel inverters (MLIs). The SVPWM method is one of the most popular real time PWM method for three phase voltage source inverter (VSI). The implementation of SVPWM method becomes complex with an increase in the number of levels in a multilevel inverter. The SVPWM method for multilevel inverter is a multitask system. The main constraint when it comes to implementing SVPWM for multilevel inverters is the processing of dwell time computation and the generation of PWM gate signals for all of the switches with an accurate delay. A hybrid hardware structure consisting of a simple low-cost, low-power dsPIC micro controller (dsPIC 30F4011) and a state of the art Field Programmable Gate Array (FPGA) (Cyclone V 5CGXFC5C6F27C7N) is used to implement SVPWM. The proposed hybrid digital architecture utilizes the advantages and resources of the dsPIC and FPGA. The hybrid digital architecture meets the timing constraints of multitasking through synchronization and parallelism. A communication interface between the dsPIC and the FPGA reduces the design complexity. The software overhead for the communication interface remains fixed for any number of levels. The hybrid structure of the digital architecture provides scalability for the SVPWM method with more number of levels in multilevel inverter. The operation of the proposed hybrid digital architecture is experimentally validated with an optimized SVPWM method for a five level VSI. An optimized region identification algorithm and simple dwell time expressions are described for a five level SVPWM. The input DC of the five level VSI is obtained from a differential power processing (DPP) based PV system. Experimental results under different operating conditions are presented.

中文翻译：

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一种用于多电平 VSI 的空间矢量 PWM 方法的高效混合数字架构

本文介绍了一种用于多电平逆变器 (MLI) 的空间矢量脉宽调制 (SVPWM) 方法的混合数字架构的高效、经济高效的设计实现。SVPWM 方法是用于三相电压源逆变器 (VSI) 的最流行的实时 PWM 方法之一。随着多电平逆变器中电平数的增加，SVPWM 方法的实现变得复杂。多电平逆变器的SVPWM方法是一个多任务系统。在为多电平逆变器实施 SVPWM 时，主要限制因素是驻留时间计算的处理以及所有具有精确延迟的开关的 PWM 门信号的生成。一种混合硬件结构，由简单的低成本、低功耗 dsPIC 微控制器 (dsPIC 30F4011) 和最先进的现场可编程门阵列 (FPGA) (Cyclone V 5CGXFC5C6F27C7N) 用于实现 SVPWM。提议的混合数字架构利用了 dsPIC 和 FPGA 的优势和资源。混合数字架构通过同步和并行满足多任务处理的时序约束。dsPIC 和 FPGA 之间的通信接口降低了设计复杂性。通信接口的软件开销对于任意数量的级别都保持固定。数字架构的混合结构为多电平逆变器中具有更多电平的 SVPWM 方法提供了可扩展性。所提出的混合数字架构的操作通过针对五级 VSI 的优化 SVPWM 方法进行了实验验证。描述了针对五级 SVPWM 的优化区域识别算法和简单的停留时间表达式。五电平 VSI 的输入 DC 是从基于差分功率处理 (DPP) 的 PV 系统获得的。给出了不同操作条件下的实验结果。